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CCD Signal Processor with Precision TimingTM Generator AD9898
FEATURES Correlated Double Sampler (CDS) 6 dB to 40 dB Variable Gain Amplifier (VGA) Black Level Clamp with Variable Level Control Complete On-Chip Timing Generator Precision Timing Core with 1 ns Resolution On-Chip: 2-Channel Horizontal and 1-Channel RG Drivers 2-Phase H-Clock Modes 4-Phase Vertical Transfer Clocks Electronic and Mechanical Shutter Modes On-Chip Sync Generator with External Sync Option Space Saving 48-Lead LFCSP Package APPLICATIONS Digital Still Cameras Digital Video Camcorders GENERAL DESCRIPTION
The AD9898 is a highly integrated CCD signal processor for digital still camera and digital video camera applications. It includes a complete analog front end with A/D conversion combined with a full function programmable timing generator. A Precision Timing core allows adjustment of high speed clocks with 1 ns resolution at 20 MHz operation. The AD9898 is specified at pixel rates as high as 20 MHz. The analog front end includes black level clamping, CDS, VGA, and a 10-bit A/D converter. The timing generator provides all the necessary CCD clocks: RG, H-clocks, V-clocks, sensor gate pulses, substrate clock, and substrate bias pulse. Operation is programmed using a 3-wire serial interface. Packaged in a space saving 48-Lead LFCSP, the AD9898 is specified over an operating temperature range of -20C to +85C.
FUNCTIONAL BLOCK DIAGRAM
REFT REFB
AD9898
6dB TO 40dB CDS VGA VREF 10 ADC DOUT
CLAMP INTERNAL CLOCKS RG 2 H1, H2 HORIZONTAL DRIVERS PRECISION TIMING GENERATOR DCLK1 FD/DCLK2 MSHUT STROBE 4 V1, V2, V3, V4 V-H CONTROL 2 VSG1, VSG2 SYNC GENERATOR INTERNAL REGISTERS
VSUB
SUBCK
HD VD SYNC
CLI
SL
SCK SDATA
REV. 0
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AD9898
TABLE OF CONTENTS FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1 FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . 1 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 DIGITAL SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 3 ANALOG SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 4 TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 5 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . 6 ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . 7 SPECIFICATION DEFINITIONS . . . . . . . . . . . . . . . . . . . 8 Differential Nonlinearity (DNL) . . . . . . . . . . . . . . . . . . . . 8 Peak Nonlinearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Total Output Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Power Supply Rejection (PSR) . . . . . . . . . . . . . . . . . . . . . . 8 EQUIVALENT INPUT CIRCUITS . . . . . . . . . . . . . . . . . . 8 TYPICAL PERFORMANCE CHARACTERISTICS . . . . . 9 SYSTEM OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 CLI INPUT CLOCK DIVIDER . . . . . . . . . . . . . . . . . . . . . 16 GRAY CODE REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . 16 SERIAL INTERFACE TIMING . . . . . . . . . . . . . . . . . . . . 17 Control Register Serial Interface . . . . . . . . . . . . . . . . . . . 17 System Register Serial Interface . . . . . . . . . . . . . . . . . . . . 17 Mode_A and Mode_B Register Serial Interface . . . . . . . . 17 VD SYNCHRONOUS AND ASYNCHRONOUS REGISTER OPERATION . . . . . . . . . . . . . . . . . . . . . . . 18 Asynchronous Register Operation . . . . . . . . . . . . . . . . . . 18 VD Synchronous Register Operation . . . . . . . . . . . . . . . . 18 ANALOG FRONT END DESCRIPTION AND OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 DC Restore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Correlated Double Sampler . . . . . . . . . . . . . . . . . . . . . . . 19 PRECISION TIMING HIGH SPEED TIMING GENERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Timing Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 High Speed Clock Programmability . . . . . . . . . . . . . . . . . 19 H-Driver and RG Outputs . . . . . . . . . . . . . . . . . . . . . . . . 20 Digital Data Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 EXTERNAL SYNCHRONIZATION (MASTER MODE) 23 HORIZONTAL AND VERTICAL SYNCHRONOUS TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Special Note About the HDLEN Register . . . . . . . . . . . . 24 HORIZONTAL CLAMPING AND BLANKING . . . . . . . 25 Controlling CLPOB Clamp Pulse Timing . . . . . . . . . . . . 25 Controlling CLPOB Clamp Pulse Outputs . . . . . . . . . . . 26 H1 AND H2 BLANKING . . . . . . . . . . . . . . . . . . . . . . . . . 27 Normal H-Blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Selective Positioning for Two H1 and H2 Outputs . . . . . 27 Extended Blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 VGATE MASKING OF V1-V4 AND CLPOB OUTPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 VERTICAL TIMING GENERATION . . . . . . . . . . . . . . . 30 Creating Vertical Sequences . . . . . . . . . . . . . . . . . . . . . . . 30 Special Vertical Sweep Mode Operation . . . . . . . . . . . . . 34 Special Vertical Timing (SPAT) . . . . . . . . . . . . . . . . . . . 35 ELECTRONIC SHUTTER TIMING CONTROL . . . . . . 37 Normal Shutter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 SUBCK Suppression Mode . . . . . . . . . . . . . . . . . . . . . . . 37 -2- High Precision Shutter Mode . . . . . . . . . . . . . . . . . . . . . . Single Pulse Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multiple Pulse Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSG TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSUB CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSUB Placement and Polarity . . . . . . . . . . . . . . . . . . . . . MSHUT CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MSHUT Basic Operation . . . . . . . . . . . . . . . . . . . . . . . . MSHUT High Precision Operation . . . . . . . . . . . . . . . . . STROBE Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SLAVE AND MASTER MODE OPERATION . . . . . . . . . Slave Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . Master Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . VARIABLE GAIN AMPLIFIER . . . . . . . . . . . . . . . . . . . . . Optical Black Clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital I/O States for Different Operating Conditions . . . POWER-UP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Power-Up Sequence for Master Mode . . . STANDBY MODE OPERATION . . . . . . . . . . . . . . . . . . . Recommended Standby Mode Sequence . . . . . . . . . . . . . POWER-DOWN MODE OPERATION . . . . . . . . . . . . . . Recommended Power-Down Sequence . . . . . . . . . . . . . . HORIZONTAL TIMING SEQUENCE EXAMPLE . . . . . CIRCUIT LAYOUT INFORMATION . . . . . . . . . . . . . . . OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 48-Lead LFCSP Package . . . . . . . . . . . . . . . . . . . . . . . . . 37 37 37 40 41 41 42 42 43 44 44 44 44 45 45 45 45 46 46 47 47 48 48 49 51 52 52
TABLES Table I. Control Register Address Map . . . . . . . . . . . . . . . . 10 Table II. System Register Address Map . . . . . . . . . . . . . . . . 12 Table III. Mode_A Register Map . . . . . . . . . . . . . . . . . . . . . 14 Table IV. Mode_B Register Map . . . . . . . . . . . . . . . . . . . . . 15 Table V. Grade Code Registers . . . . . . . . . . . . . . . . . . . . . . 16 Table VI. Type of Serial Interface Registers . . . . . . . . . . . . 17 Table VII. AFE Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table VIII. RG, H1, SHP, SHD, DCLK, and DOUTPHASE Timing Parameters . . . . . . . . . . . . . . . . . 21 Table IX. Precision Timing Edge Locations for RG, H1, SHP, SHD, DCLK, and DOUTPHASE . . . . . . . . . . . . . . . . . . 21 Table X. External Synchronization (Master Mode) . . . . . . . 23 Table XI. HD and VD Registers . . . . . . . . . . . . . . . . . . . . . 24 Table XII. CLPOB Registers . . . . . . . . . . . . . . . . . . . . . . . . 25 Table XIII. SCP and CLPEN . . . . . . . . . . . . . . . . . . . . . . . 26 Table XIV. H1 Blanking Registers . . . . . . . . . . . . . . . . . . . . 27 Table XV. V1-V4 Registers to Configure V1-V4 Pulse for Each VTP Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table XVI. Mode_A and Mode_B Registers for VTPx Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table XVII. Mode_A and Mode_B Registers for CCD Region Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table XVIII. Description of SVREP_MODE Register . . . . 34 Table XIX. HD and VD Registers . . . . . . . . . . . . . . . . . . . . 35 Table XX. SPATLOGIC Register . . . . . . . . . . . . . . . . . . . . 35 Table XXI. SUBCK Registers . . . . . . . . . . . . . . . . . . . . . . . 37 Table XXII. Single and Multiple Pulse Mode . . . . . . . . . . . 37 Table XXIII. VSG Registers . . . . . . . . . . . . . . . . . . . . . . . . 40 Table XXIV. VSUB Registers . . . . . . . . . . . . . . . . . . . . . . . 41 Table XXV. MSHUT and STROBE Registers . . . . . . . . . . 42 Table XXVI. I/O Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 REV. 0
AD9898
SPECIFICATIONS
Parameter TEMPERATURE RANGE Operating Storage POWER SUPPLY VOLTAGE AVDD (AFE Analog Supply) TCVDD (Timing Core Analog Supply) RGVDD (RG Driver) HVDD (H1-H2 Drivers) DRVDD (Data Output Drivers) DVDD (Digital) POWER DISSIPATION 20 MHz, Typical Supply Levels, 100 pF H1-H2 Loading Power from HVDD Only* Power-Down Mode (AFE and Digital in Standby Operation) MAXIMUM CLOCK RATE (CLI) AD9898 20 Min -20 -65 2.7 2.7 2.7 2.7 2.7 2.7 3.0 3.0 3.0 3.0 3.0 3.0 150 36 3 Typ Max +85 +150 3.6 3.6 3.6 3.6 3.6 3.6 Unit C C V V V V V V mW mW mW MHz
*The total power dissipated by the HVDD supply may be approximated using the equation Total HVDD Power = (CLOAD x HVDD x Pixel Frequency) x HVDD x Number of H-Outputs Used Actual HVDD power may be slightly higher than the calculated value because of stray capacitance inherent in the PCB layout/routing. Specifications subject to change without notice.
DIGITAL SPECIFICATIONS
Parameter LOGIC INPUTS High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Capacitance
(RGVDD = HVDD = 2.7 V to 3.6 V, DVDD = DRVDD = 2.7 V to 3.6 V, CL = 20 pF, TMIN to TMAX, unless otherwise noted.)
Symbol VIH VIL IIH IIL CIN VOH VOL VOH VOL Min 2.1 0.6 10 10 10 2.2 0.5 VDD - 0.5 0.5 15 30 100 Typ Max Unit V V A A pF V V V V mA mA pF
LOGIC OUTPUTS (Except H and RG) High Level Output Voltage @ IOH = 2 mA Low Level Output Voltage @ IOL = 2 mA RG and H-DRIVER OUTPUTS (H1-H2) High Level Output Voltage @ Maximum Current Low Level Output Voltage @ Maximum Current RG Maximum Output Current (Programmable) H1 and H2 Maximum Output Current (Programmable) Maximum Load Capacitance
Specifications subject to change without notice.
REV. 0
-3-
AD9898 ANALOG SPECIFICATIONS
Parameter
(AVDD = 3.0 V, fCLI = 20 MHz, TMIN to TMAX, unless otherwise noted.)
Min Typ 500 100 Max Unit mV V p-p mV V p-p Steps Comments Input Signal Characteristics
CDS Allowable CCD Reset Transient Maximum Input Range before Saturation* 1.0 Maximum CCD Black Pixel Amplitude VARIABLE GAIN AMPLIFIER (VGA) Maximum Output Range Gain Control Resolution Gain Monotonicity Gain Range Low Gain Maximum Gain BLACK LEVEL CLAMP Clamp Level Resolution Clamp Level Minimum Clamp Level Maximum Clamp Level A/D CONVERTER Resolution Differential Nonlinearity (DNL) No Missing Codes Full-Scale Input Voltage VOLTAGE REFERENCE Reference Top Voltage (REFT) Reference Bottom Voltage (REFB) SYSTEM PERFORMANCE Gain Accuracy Low Gain (VGA Code = 20) Maximum Gain (VGA Code = 991) Peak Nonlinearity, 500 mV Input Signal Total Output Noise Power Supply Rejection (PSR)
*Input signal characteristics defined as follows:
500mV TYP RESET TRANSIENT
2.0 1024 Guaranteed 6 40 64 0 63 10 0.5 Guaranteed 2.0 2.0 1.0
dB dB Steps LSB LSB LSB Bits LSB V V V Includes entire signal chain
LSB is measured at ADC output.
5 39
6 40 0.1 0.3 40
7 41
dB dB % LSB rms dB
Gain = (0.035 x Code) + 5.3 dB 12 dB gain applied AC grounded input, 6 dB gain applied Measured with step change on supply
100mV MAX OPTICAL BLACK PIXEL
1V MAX INPUT SIGNAL RANGE
Specifications subject to change without notice.
-4-
REV. 0
AD9898 TIMING SPECIFICATIONS
Parameter MASTER CLOCK, CLI CLI Clock Period CLI High/Low Pulsewidth Delay from CLI Rising Edge to Internal Pixel Position 0 AFE CLAMP PULSES* CLPOB Pulsewidth AFE SAMPLE LOCATION* (See Figure 13) SHP Sample Edge to SHD Sample Edge DATA OUTPUTS (See Figure 15) Output Delay from DCLK Rising Edge Pipeline Delay from SHP/SHD Sampling SERIAL INTERFACE (See Figures 7 and 8) Maximum SCK Frequency SL to SCK Setup Time SCK to SL Hold Time SDATA Valid to SCK Rising Edge Setup SCK Falling Edge to SDATA Valid Hold SCK Falling Edge to SDATA Valid Read
*Parameter is programmable. Specifications subject to change without notice.
(CL = 20 pF, AVDD = DVDD = DRVDD = 3.0 V, fCLI = 20 MHz, unless otherwise noted.)
Symbol tCONV tCLIDLY 4 tS1 tOD 20 Min 50 20 Typ Max Unit ns ns ns Pixels Pixels ns Cycles MHz ns ns ns ns ns
25 6 10 25 9 9
fSCLK tLS tLH tDS tDH tDV
10 10 10 10 10 10
REV. 0
-5-
AD9898
ABSOLUTE MAXIMUM RATINGS*
Parameter AVDD TCVDD HVDD RGVDD DVDD DRVDD RG Output H1-H2 Output Digital Outputs Digital Inputs SCK, SL, SDATA REFT, REFB CCDIN Junction Temperature Lead Temperature, 10 sec
With Respect To AVSS TCVSS HVSS RGVSS DVSS DRVSS RGVSS HVSS DVSS DVSS DVSS AVSS AVSS
Min -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3
Max +3.9 +3.9 +3.9 +3.9 +3.9 +3.9 RGVDD + 0.3 HVDD + 0.3 DVDD + 0.3 DVDD + 0.3 DVDD + 0.3 AVDD + 0.3 AVDD + 0.3 150 300
Unit V V V V V V V V V V V V V C C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
PACKAGE THERMAL CHARACTERISTICS Thermal Resistance
JA
= 92C/W
ORDERING GUIDE
Model AD9898KCP-20 AD9898KCPRL-20
Temperature Range -20C to +85C -20C to +85C
Package Description Lead Frame Chip Scale Package (LFCSP) Lead Frame Chip Scale Package (LFCSP)
Package Option CP-48 CP-48
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9898 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
-6-
REV. 0
AD9898
PIN CONFIGURATION
SYNC/VGATE OUTCONT SUBCK
VSUB
DVDD
VSG2
VSG1
DVSS
V4
V3
V2
48 47 46 45 44 43 42 41 40 39 38 37
D0 1 D1 2 D2 3 D3 4 D4 5 DRVSS 6 DRVDD 7 D5 8 D6 9 D7 10 D8 11 D9 12
V1
36 SCK 35 SL 34 SDATA 33 REFB 32 REFT 31 AVSS 30 CCDIN 29 AVDD 28 CLI 27 TCVDD 26 TCVSS 25 RGVDD
PIN 1 IDENTIFIER
AD9898
TOP VIEW (Not to Scale)
13 14 15 16 17 18 19 20 21 22 23 24
DCLK1
STROBE
FD/DCLK2
MSHUT
PIN FUNCTION DESCRIPTION
Pin No. Mnemonic 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 REV. 0 D0 D1 D2 D3 D4 DRVSS DRVDD D5 D6 D7 D8 D9 DCLK1 MSHUT STROBE FD/ DCLK2 HD VD HVDD HVSS H2 H1 RGVSS RG RGVDD TCVSS TCVDD
Type* Description DO DO DO DO DO P P DO DO DO DO DO DO DO DO DO DO DI DI P P DO DO P DO P P P Data Output Data Output Data Output Data Output Data Clock Output Data Output Driver Ground Data Output Driver Supply Data Output Data Output Data Output Data Output Data Output Data Clock Output Mechanical Shutter Pulse Strobe Pulse Field Designator Output DCLK2 Output Horizontal Sync Pulse Vertical Sync Pulse H1-H2 Driver Supply H1-H2 Driver Ground CCD Horizontal Clock 2 CCD Horizontal Clock 1 RG Driver Ground CCD Reset Gate Clock RG Driver Supply Analog Ground for Timing Core Analog Supply for Timing Core -7-
Pin No. Mnemonic 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 CLI AVDD CCDIN AVSS REFT REFB SDATA SL SCK V1 V2 V3 V4 VSG1 VSG2 VSUB SYNC/ VGATE DVDD
RGVSS
HVDD
HVSS
RG
HD
H2
VD
H1
Type* Description DI P AI P AO AO DI DI DI DO DO DO DO DO DO DO DI DI P Reference Clock Input Analog Supply for AFE CCD Input Signal Analog Ground for AFE Voltage Reference Top Bypass Voltage Reference Bottom Bypass 3-Wire Serial Data Input 3-Wire Serial Load Pulse 3-Wire Serial Clock CCD Vertical Transfer Clock 1 CCD Vertical Transfer Clock 2 CCD Vertical Transfer Clock 3 CCD Vertical Transfer Clock 4 CCD Sensor Gate Pulse 1 CCD Sensor Gate Pulse 2 Output Control CCD Substrate Bias External System Sync Input VGATE Input Digital Supply for VSG, V1-V4, HD, VD, MSHUT, STROBE, and Serial Interface Digital Ground CCD Substrate Clock (E-Shutter)
OUTCONT DI
47 48
DVSS SUBCK
P DO
*AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, P = Power.
AD9898
SPECIFICATION DEFINITIONS Differential Nonlinearity (DNL) Total Output Noise
An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Thus every code must have a finite width. No missing codes guaranteed to 10-bit resolution indicates that all 1024 codes, respectively, must be present over all operating conditions.
Peak Nonlinearity
The rms output noise is measured using histogram techniques. The standard deviation of the ADC output codes is calculated in LSB and represents the rms noise level of the total signal chain at the specified gain setting. The output noise can be converted to an equivalent voltage, using the relationship 1 LSB = (ADC Full Scale/2N codes) where N is the bit resolution of the ADC. For the AD9898, 1 LSB is 2 mV.
Power Supply Rejection (PSR)
Peak nonlinearity, a full signal chain specification, refers to the peak deviation of the output of the AD9898 from a true straight line. The point used as zero scale occurs 1/2 LSB before the first code transition. Positive full scale is defined as a level 1 1/2 LSB beyond the last code transition. The deviation is measured from the middle of each particular output code to the true straight line. The error is then expressed as a percentage of the 2 V ADC full-scale signal. The input signal is always appropriately gained up to fill the ADC's full-scale range.
The PSR is measured with a step change applied to the supply pins. The PSR specification is calculated from the change in the data outputs for a given step change in the supply voltage.
EQUIVALENT INPUT CIRCUITS
DVDD
AVDD
330
R
AVSS
AVSS
DVSS
Figure 1. CCDIN
Figure 3. Digital Inputs
DVDD
DRVDD
RG, H1-H2
HVDD OR RGVDD
DATA
THREESTATE
DOUT
ENABLE
OUTPUT
DVSS
HVSS OR RGVSS
DRVSS
Figure 2. Digital Data Outputs
Figure 4. H1-H2, RG Drivers
-8-
REV. 0
Typical Performance Characteristics-AD9898
180
0.3
160 POWER DISSIPATION (mW)
VDD = 3.3V
0.15
140
DNL (LSB)
VDD = 3.0V 120
0
100 VDD = 2.7V 80
-0.3 -0.15
60 10
15 SAMPLE RATE - MHz
20
0
200
400 CODE
600
800
1000
TPC 1. Power vs. Sample Rate
TPC 2. Typical DNL Performance
REV. 0
-9-
AD9898
Table I. Control Register Address Map (Register Names Are Subject to Change)
Address 00 01 Content (23:0) (23:21) 20 (19:18) 17 16 (15:14) 13 12 (11:10) (9:8) 7 6 5 4 (3:1) 0 02 (23:22) (21:16) (15:14) (13:8) (7:6) (5:0) (23:17) 16 (15:14) (13:8) (7:6) (5:0) (23:22) (21:16) (14:12) 11 (10:8) (7:3) (2:0) 05 (23:10) 9 8 (7:2) 1 0 Bit Width 23 3 1 2 1 1 2 1 1 2 2 1 1 1 1 3 1 2 6 2 6 2 6 7 1 2 6 2 6 2 6 3 1 3 5 3 14 1 1 6 1 1 Default Value 000000 0 0 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0x34 0 0x18 0 0x0B 0x00 0 0 0x00 0 0x10 0 0x20 5 0 5 0x00 2 0x0000 0 0 00 0 1 Register Name SW_RESET Register Description Software Reset = 000000. (Reset all registers to default.) Unused Unused. Test Mode. Should be set = 0. Unused Masking Polarity for H1 during blanking period (0 = Low, 1 = High) External SYNC Active Polarity (0 = Active Low) Unused High Precision Shutter Mode Operation (0 = Single Pulse, 1 = Multiple Pulse) Suppress First SUBCK after Last VSG Line Pulse (0 = No Suppression, 1 = Suppression of 1 SUBCK) Unused Selects MSHUT Pattern (See Figure 44) (0 = MSHUTPAT0, 1 = MSHUTPAT1, 2 = MSHUTPAT2, 3 = MSHUTPAT3) MSHUT Masking of VGATE Input (0 = MSHUT does not mask VGATE, 1 = MSHUT does mask VGATE) MSHUT Masking of SUBCK (0 = MSHUT does not mask SUBCK, 1 = MSHUT does mask SUBCK) CLPOB Control (0 = CLPOB OFF, 1 = CLPOB ON) CLPOB CCD Region Control (See Table XII) Unused VD Synchronous/Asynchronous Mode Setting (0 = VD Synchronous, 1 = VD Asynchronous) Unused SHD Sample Location Unused SHP Sample Location DCLK Pulse Adjustment Data Output [9:0] Phase Adjustment Unused Retimes the H1 HBLK to Internal Clock Unused H1 Positive Edge Location Unused RG Negative Edge Location Unused Black Clamp Level H2 Drive Strength (0 = Off, 1 = 4.3 mA, 2 = 8.6 mA, 3 = 12.9 mA, 4 = 17.2 mA, 5 = 21.5 mA, 6 = 25.8 mA, 7 = 30.1 mA) Unused H1 Drive Strength (0 = Off, 1 = 4.3 mA, 2 = 8.6 mA, 3 = 12.9 mA, 4 = 17.2 mA, 5 = 21.5 mA, 6 = 25.8 mA, 7 = 30.1 mA) Unused RG Drive Strength (0 = Off, 1 = 2.15 mA, 2 = 4.2 mA, 3 = 6.45 mA, 4 = 8.6 mA, 5 = 10.75 mA, 6 = 12.9 mA, 7 = 15.05 mA) Unused AFE Standby (0 = Standby , 1 = Normal Operation) Digital Standby (0 = Standby , 1 = Normal Operation) Unused Internal OUTCONT Signal Control (0 = Digital Outputs held at fixed dc level, 1 = Normal Operation) External OUTCONT Signal Input Pin 43 Control (0 = Pin Enabled, 1 = Pin Disabled)
HBLKMASK SYNCPOL SUBCKMODE_HP SUBCKSUPPRESS
MSHUTPAT MSHUT/VGATE_EN MSHUT/SUBCK_EN CLP_CONT CLP_MODE VDMODE
SHDLOC SHPLOC DCLKPHASE DOUTPHASE H1BLKRETIME H1POSLOC RGNEGLOC REFBLACK H2DRV
03
04
H1DRV
RGDRV
AFESTBY DIGSTBY OUTCONT_REG OUTCONT_ENB
-10-
REV. 0
AD9898
Table I. Control Register Address Map (Register Names Are Subject to Change)
Address 0A Content Bit Width 1 1 6 4 2 1 1 4 2 1 1 2 1 1 3 1 1 3 1 11 3 1 2 1 1 1 3 1 11 7 1 5 11 3 1 2 1 1 6 10 20 1 1 2 23 1 Default Value 0 0 0x00 0 0 0 0 C 3 0 0 0 1 1 0 0 0 0 0 0x7FF 0 0 0 0 0 0 0 0 0x000 0 0x000 0 0 0 0 0 0x00 0x000 0x00000 1 0 0 Register Name FDPOL VSGMASK SYNCCNT SVREP_MODE HBLKEXT HPULSECNT SPATLOGIC SVOS SPAT_EN MODE SUBCK_EN VSG_EN STROBE_EN Register Description Unused FD Polarity Control (0 = Low, 1 = High) VSG Masking (See Table XXIII) External SYNC Setting Super Vertical Repetition Mode H Pulse Blanking Extend Control H Pulse Control during Blanking SPAT Logic Setting (See Table XX) Second V Output Setting (10 = Output Repetition 1) SPAT Control (0 = SPAT Disable, 1 = SPAT Enable) Mode Control Bit (0 = Mode_A, 1 = Mode_B) Unused SUBCK Output Enable Control (0 = Disable, 1 = Enable) VSG Output Enable Control (0 = Disable, 1 = Enable) Unused STROBE Output Control (0 = STROBE Output Held Low, 1 = STROBE Output Enabled) Unused High Precision Shutter SUBCLK Pulse Position/Number Unused Total Number of SUBCKs per Field Unused MSHUT Initialize (1 = Forces MSHUT Low) Unused Unused MSHUT Control ( 0 = MSHUT Held at Last State, 1 = MSHUT Output) Unused MSHUT Position during High Precision Operation Unused MSHUT Position during Normal Operation Unused VSUB Active Polarity (0 = Low, 1 = High) Unused VSUB Toggle Position. Active starting line in any field. Unused Unused. Test Mode. Should be set = 0. Unused Unused. Test Mode. Should be set = 0. Unused. Test Mode. Should be set = 0. Unused VGA Gain Unused DCLK2 Selector (0 = Select Internal FD Signal to be Output on FD/ DCLK2 Pin 16, 1 = Select CLI to be Output on FD/DCLK2 Pin 16) DCLK1 Selector (0 = Select DLL Version for DCLK1 Output, 1 = Select CLI for DCLK1 Output) Input Clock Divider (0 = No Division, 1 = 1/2, 2 = 1/3, 3 = 1/4) Unused Operating Mode ( 0 = Master Mode, 1 = Slave Mode)
23 22 (21:16) (15:12) (VD (11:10) SyncReg)* 9 8 (7:4) (3:2) 1 0 0B (23:22) 21 20 (VD (19:17) SyncReg)* 16 15 (14:12) 11 (10:0) (23:21) 20 (19:18) (VD 17 SyncReg)* 16 15 (14:12) 11 (10:0) (23:17) 16 (VD (15:11) SyncReg)* (10:0) 0E (23:21) 20 (19:18) (VD 17 SyncReg)* 16 (15:10) (9:0) D5 (23:4) 3 2 (1:0) D6 (23:1) 0 0D 0C
SUBCKNUM_HP SUBCKNUM MSHUTINIT
MSHUTEN MSHUTPOS_HP MSHUTPOS VSUBPOL VSUBTOG
VGAGAIN DCLK2SEL DCLK1SEL CLKDIV
0x000000 1 SLAVE_MODE
*This register defaults to VD synchronous mode type at power up. VD sync type registers do not get updated until the first falling edge of VD is asserted after the register has been programmed. VD sync type registers can be programmed to be asynchronous registers by setting VDMODE = 1 (Addr 0x01).
REV. 0
-11-
AD9898
Table II. System Register Address Map (Addr 0x14)
Register Sys_Reg(0) Sys_Reg(1)
Content (31:24) (23:0) (31:23) 22 21 20 19 (18:10) (9:1) 0 (31:24) (23:15) (14:6) (5:0) (31:29) (28:20) (19:11) (10:2) 1 0 31 30 (29:21) (20:12) (11:3) (2:0) (31:26) (25:17) (16:8) (7:0) 31 (30:22) (21:13) 12 11 10 9 (8:0) (31:23) (22:14) (13:5) (4:0) (31:28) (27:19) (18:10) (9:1) 0
Bit Default Width (Decimal) Register Name 8 24 9 1 1 1 1 9 9 1 8 9 9 6 3 9 9 9 1 1 1 1 9 9 9 3 6 9 9 8 1 9 9 1 1 1 1 9 9 9 9 5 4 9 9 9 1 NA NA 37 0 0 1 1 0 19 0 12 31 0 19 12 31 104 0 0 1 1 18 58 47 96 0 76 38 105 57 0 0 1 1 0 29 19 48 0 29 19 48 System_Reg_Addr System_Number_N VTPLEN0 V1STARTPOL0 V2STARTPOL0 V3STARTPOL0 V4STARTPOL0 V1TOG1POS0 V1TOG2POS0 V2TOG1POS0 [8] V2TOG1POS0 [7:0] V2TOG2POS0 V3TOG1POS0 V3TOG2POS0 [8:3] V3TOG2POS0 [2:0] V4TOG1POS0 V4TOG2POS0 VTPLEN1 V1STARTPOL1 V2STARTPOL1 V3STARTPOL1 V4STARTPOL1 V1TOG1POS1 V1TOG2POS1 V2TOG1POS1 V2TOG2POS1 [8:6] V2TOG2POS1 [5:0] V3TOG1POS1 V3TOG2POS1 V4TOG1POS1 [8:1] V4TOG1POS1 [0] V4TOG2POS1 VTPLEN2 V1STARTPOL2 V2STARTPOL2 V3STARTPOL2 V4STARTPOL2 V1TOG1POS2 V1TOG2POS2 V2TOG1POS2 V2TOG2POS2 V3TOG1POS2 [8:4] V3TOG1POS2 [3:0] V3TOG2POS2 V4TOG1POS2 V4TOG2POS2
Register Description System Register Address Is (Addr 0x14) Number N Register Writes (0x000000 = Write All Registers) Vertical Sequence No. 0: Length between Repetitions Vertical Sequence No. 0: V1 Start Polarity Vertical Sequence No. 0: V2 Start Polarity Vertical Sequence No. 0: V3 Start Polarity Vertical Sequence No. 0: V4 Start Polarity Vertical Sequence No. 0: V1 Toggle Position 1 Vertical Sequence No. 0: V1 Toggle Position 2 Vertical Sequence No. 0: V2 Toggle Position 1 Vertical Sequence No. 0: V2 Toggle Position 2 Vertical Sequence No. 0: V3 Toggle Position 1 Vertical Sequence No. 0: V3 Toggle Position 2 Vertical Sequence No. 0: V4 Toggle Position 1 Vertical Sequence No. 0: V4 Toggle Position 2 Vertical Sequence No. 1: Length between Repetitions Vertical Sequence No. 1: V1 Start Polarity Vertical Sequence No. 1: V2 Start Polarity Vertical Sequence No. 1: V3 Start Polarity Vertical Sequence No. 1: V4 Start Polarity Vertical Sequence No. 1: V1 Toggle Position 1 Vertical Sequence No. 1: V1 Toggle Position 2 Vertical Sequence No. 1: V2 Toggle Position 1 Vertical Sequence No. 1: V2 Toggle Position 2 Vertical Sequence No. 1: V3 Toggle Position 1 Vertical Sequence No. 1: V3 Toggle Position 2 Vertical Sequence No. 1: V4 Toggle Position 1 Vertical Sequence No. 1: V4 Toggle Position 2 Vertical Sequence No. 2: Length between Repetitions Vertical Sequence No. 2: V1 Start Polarity Vertical Sequence No. 2: V2 Start Polarity Vertical Sequence No. 2: V3 Start Polarity Vertical Sequence No. 2: V4 Start Polarity Vertical Sequence No. 2: V1 Toggle Position 1 Vertical Sequence No. 2: V1 Toggle Position 2 Vertical Sequence No. 2: V2 Toggle Position 1 Vertical Sequence No. 2: V2 Toggle Position 2 Vertical Sequence No. 2: V3 Toggle Position 1 Vertical Sequence No. 2: V3 Toggle Position 2 Vertical Sequence No. 2: V4 Toggle Position 1 Vertical Sequence No. 2: V4 Toggle Position 2 Unused
Sys_Reg(2)
Sys_Reg(3)
Sys_Reg(4)
Sys_Reg(5)
Sys_Reg(6)
Sys_Reg(7)
Sys_Reg(8)
-12-
REV. 0
AD9898
Table II. System Register Address Map (Addr 0x14) (continued)
Register Sys_Reg(9)
Content (31:23) 22 21 20 19 (18:10) (9:1) 0 (31:24) (23:15) (14:6) (5:0) (31:29) (28:20) (19:11) (10:1) 0 (31:20) (19:10) (9:1) 0 (31:24) (23:16) (15:5) (4:0) (31:26) (25:18) (17:9) (8:0) (31:23) (22:14:) (13:2) (1:0) (31:22) (21:18) (17:8) (7:0)
Bit Default Width (Decimal) Register Name 9 1 1 1 1 9 9 1 8 9 9 6 3 9 9 10 1 12 10 9 1 8 8 11 5 6 8 9 9 9 9 12 2 10 4 10 8 89 0 0 1 1 0 60 30 90 0 60 30 90 0 2283 130 100 0 118 1048 1198 60 19 88 19 88 2243 2278 9 120 VTPLEN3 V1STARTPOL3 V2STARTPOL3 V3STARTPOL3 V4STARTPOL3 V1TOG1POS3 V1TOG2POS3 V2TOG1POS3 [8] V2TOG1POS3 [7:0] V2TOG2POS3 V3TOG1POS3 V3TOG2POS3 [8:3] V3TOG2POS3 [2:0] V4TOG1POS3 V4TOG2POS3 HBLKHPOS HDLEN* HLEN OLEN BLLEN [8] BLLEN[7:0] MSHUTLEN VSGTOG1_0 VSGTOG1_1 [10:6] VSGTOG1_1 [5:0] VSGLEN SUBCK1TOG1 SUBCK1TOG2 SUBCK2TOG1 SUBCK2TOG2 CLPTOG1* CLPTOG2 [11]* CLPTOG2 [10:0]* VDRISE HDRISE
Register Description Vertical Sequence No. 3: Length between Repetitions Vertical Sequence No. 3: V1 Start Polarity Vertical Sequence No. 3: V2 Start Polarity Vertical Sequence No. 3: V3 Start Polarity Vertical Sequence No. 3: V4 Start Polarity Vertical Sequence No. 3: V1 Toggle Position 1 Vertical Sequence No. 3: V1 Toggle Position 2 Vertical Sequence No. 3: V2 Toggle Position 1 Vertical Sequence No. 3: V2 Toggle Position 2 Vertical Sequence No. 3: V3 Toggle Position 1 Vertical Sequence No. 3: V3 Toggle Position 2 Vertical Sequence No. 3: V4 Toggle Position 1 Vertical Sequence No. 3: V4 Toggle Position 2 H1 Pulse ON Position during Blanking Period Unused 12-Bit Gray Code HD Counter Value (Gray Code Number) 10-Bit HL Counter Value 9-Bit OL Counter Value 9-Bit BL Counter Value MSHUT Sequence Length VSG Sequence No. 1 Toggle Position 1 VSG Sequence No. 2 Toggle Position 1 VSG Pulsewidth SUBCK1 First Toggle Position SUBCK1 Second Toggle Position SUBCK2 First Toggle Position SUBCK2 Second Toggle Position CLPOB Toggle Position No. 1 CLPOB Toggle Position No. 2 VD Toggle Position No. 1 HD Toggle Position No. 2 Unused
Sys_Reg(10)
Sys_Reg(11)
Sys_Reg(12)
Sys_Reg(13)
Sys_Reg(14)
Sys_Reg(15)
Sys_Reg(16)
*Register value must be a gray code number. (See Gray Code Registers section.)
REV. 0
-13-
AD9898
Table III. Mode_A Register Map (Addr 0x15)
Register
Content
Bit Default Width (Decimal) Register Name 8 24 11 12 1 1 7 1 3 3 3 3 3 1 1 1 1 1 8 3 5 8 8 2 2 2 2 3 3 3 3 11 11 1 13 13 6 7 13 12 1 13 13 5 8 13 2 9 NA NA 262 1139 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 3 0 0 0 0 0 988 1138 1078 1168 958 1138 988 1228 1392 3
Register Description
Mode_Reg(0) (31:24) (23:0) Mode_Reg(1) (31:21) (20:9) 8 7 (6:0) Mode_Reg(2) 31 (30:28) (27:25) (24:22) (21:19) (18:16) 15 14 13 12 11 (10:3) (2:0) Mode_Reg(3) (31:27) (26:19) (18:11) (10:9) (8:7) (6:5) (4:3) (2:0) Mode_Reg(4) (31:29) (28:26) (25:23) (22:12) (11:1) 0 Mode_Reg(5) (31:19) (18:6) (5:0) Mode_Reg(6) (31:25) (24:12) (11:0) Mode_Reg(7) 31 (30:18) (17:5) (4:0) Mode_Reg(8) (31:24) (23:11) (10:9) (8:0)
Mode_A_Addr Mode_A Address Is (Addr 0x15) Mode_A_Number_N Number N Register Writes (0x000000 = Write All Registers) VDLEN HDLASTLEN VSGSEL0 VSGSEL1 VSGACTLINE SUBCKSEL VTPSEQPTR0 VTPSEQPTR1 VTPSEQPTR2 VTPSEQPTR3 VTPSEQPTR4 CLPEN0 CLPEN1 CLPEN2 CLPEN3 CLPEN4 SCP1 SCP2 SCP2 SCP3 SCP4 VTPSEL0 VTPSEL1 VTPSEL2 VTPSEL3 VTPREP0 VTPREP1 VTPREP2 VTPREP3 SVREP0 SVREP3 V1SPAT_TOG1 V1SPAT_TOG2 V2SPAT_TOG1 V2SPAT_TOG1 V2SPAT_TOG2 V3SPAT_TOG1 V3SPAT_TOG1 V3SPAT_TOG2 V4SPAT_TOG1 V4SPAT_TOG2 V4SPAT_TOG2 SECONDVPOS VPATSECOND VD Counter Value Number of Pixels in Last Line (Gray Code Number) VSG1 Sequence Selector (See Table XXIII) VSG2 Sequence Selector (See Table XXIII) VSG Active Line Select one of two SUBCK Patterns Vertical Transfer Sequence Region No. 0 Vertical Transfer Sequence Region No. 1 Vertical Transfer Sequence Region No. 2 Vertical Transfer Sequence Region No. 3 Vertical Transfer Sequence Region No. 4 CLPOB Output Control No. 1 CLPOB Output Control No. 2 CLPOB Output Control No. 3 CLPOB Output Control No. 4 CLPOB Output Control No. 5 Sequence Change Position No. 1 Sequence Change Position No. 2 Sequence Change Position No. 3 Sequence Change Position No. 4 Vertical Pattern Selection 0 Vertical Pattern Selection 1 Vertical Pattern Selection 2 Vertical Pattern Selection 3 Number of Vertical Pulse Repetitions for Pattern0 Number of Vertical Pulse Repetitions for Pattern1 Number of Vertical Pulse Repetitions for Pattern2 Number of Vertical Pulse Repetitions for Pattern3 Vertical Sweep Repetition Number for CCD Region0 Vertical Sweep Repitition Number for CCD Region3 Unused Polarity Change Position Start for V1 SPAT Polarity Change Position End for V1 SPAT Polarity Change Position Start for V2 SPAT Polarity Change Position End for V2 SPAT Polarity Change Position Start for V3 SPAT Polarity Change Position End for V3 SPAT Polarity Change Position Start for V4 SPAT Polarity Change Position End for V4 SPAT Second V Pattern Output Position Selected Second V Pattern Group for VSG Active Line Unused
-14-
REV. 0
AD9898
Table IV. Mode_B Register Map (Addr 0x16)
Register
Content
Bit Default Width (Decimal) Register Name 8 24 11 12 1 1 7 1 3 3 3 3 3 1 1 1 1 1 8 3 5 8 8 2 2 2 2 3 3 3 3 11 11 1 13 13 6 7 13 12 1 13 13 5 8 13 2 9 NA NA 262 1139 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 3 0 0 0 0 0 988 1138 1078 1168 958 1138 988 1228 1392 3
Register Description
Mode_Reg(0) (31:24) (23:0) Mode_Reg(1) (31:21) (20:9) 8 7 (6:0) Mode_Reg(2) 31 (30:28) (27:25) (24:22) (21:19) (18:16) 15 14 13 12 11 (10:3) (2:0) Mode_Reg(3) (31:27) (26:19) (18:11) (10:9) (8:7) (6:5) (4:3) (2:0) Mode_Reg(4) (31:29) (28:26) (25:23) (22:12) (11:1) 0 Mode_Reg(5) (31:19) (18:6) (5:0) Mode_Reg(6) (31:25) (24:12) (11:0) Mode_Reg(7) 31 (30:18) (17:5) (4:0) Mode_Reg(8) (31:24) (23:11) (10:9) (8:0)
Mode_B_Addr Mode_B Address Is (Addr 0x16) Mode_B_Number_N Number N Register Writes (0x000000 = Write All Registers) VDLEN HDLASTLEN* VSGSEL0 VSGSEL1 VSGACTLINE SUBCKSEL VTPSEQPTR0 VTPSEQPTR1 VTPSEQPTR2 VTPSEQPTR3 VTPSEQPTR4 CLPEN0 CLPEN1 CLPEN2 CLPEN3 CLPEN4 SCP1 SCP2 SCP2 SCP3 SCP4 VTPSEL0 VTPSEL1 VTPSEL2 VTPSEL3 VTPREP0 VTPREP1 VTPREP2 VTPREP3 SVREP0 SVREP3 V1SPAT_TOG1 V1SPAT_TOG2 V2SPAT_TOG1 V2SPAT_TOG1 V2SPAT_TOG2 V3SPAT_TOG1 V3SPAT_TOG1 V3SPAT_TOG2 V4SPAT_TOG1 V4SPAT_TOG2 V4SPAT_TOG2 SECONDVPOS VPATSECOND VD Counter Value Number of Pixels in Last Line (Gray Code Number) VSG1 Sequence Selector (See Table XXIII) VSG2 Sequence Selector (See Table XXIII) VSG Active Line Select One of Two SUBCK Patterns Vertical Transfer Sequence Region No. 0 Vertical Transfer Sequence Region No. 1 Vertical Transfer Sequence Region No. 2 Vertical Transfer Sequence Region No. 3 Vertical Transfer Sequence Region No. 4 CLPOB Output Control No. 1 CLPOB Output Control No. 2 CLPOB Output Control No. 3 CLPOB Output Control No. 4 CLPOB Output Control No. 5 Sequence Change Position No. 1 Sequence Change Position No. 2 Sequence Change Position No. 3 Sequence Change Position No. 4 Vertical Pattern Selection 0 Vertical Pattern Selection 1 Vertical Pattern Selection 2 Vertical Pattern Selection 3 Number of VTP0 Pulse Repetitions for Pattern0 Number of VTP1 Pulse Repetitions for Pattern1 Number of VTP2 Pulse Repetitions for Pattern2 Number of VTP0 Pulse Repetitions for Pattern3 Vertical Sweep Repetition Number for CCD Region0 Vertical Sweep Repetition Number for CCD Region3 Unused Polarity Change Position Start for V1 SPAT Polarity Change Position End for V1 SPAT Polarity Change Position Start for V2 SPAT Polarity Change Position End for V2 SPAT Polarity Change Position Start for V3 SPAT Polarity Change Position End for V3 SPAT Polarity Change Position Start for V4 SPAT Polarity Change Position End for V4 SPAT Second V Pattern Output Position Selected Second V Pattern Group for VSG Active Line Unused
*Register value must be a gray code number. (See Gray Code Registers section.)
REV. 0
-15-
AD9898
SYSTEM OVERVIEW
MAXIMUM FIELD DIMENSIONS
V1-V4, VSG1, VSG2, SUBCK V-DRIVER H1, H2, RG, VSUB DOUT[9:0] CCD CCDIN DCLK1 FD
Figure 6. Horizontal and Vertical Counters
CLI INPUT CLOCK DIVIDER
DIGITAL IMAGE PROCESSING ASIC
AD9898
MSHUT STROBE
HD, VD VGATE CLI
SERIAL INTERFACE
SYNC P
OUTCONT
The AD9898 provides the capability of dividing the CLI input clock using register CLKDIV (Addr 0xD5). The following procedure must be followed to reset the AFE and digital circuits when CLKDIV is reprogrammed back to 0 from CLKDIV = 1, 2, or 3. The DCLK1 output will become unstable if this procedure is not followed: Step 1: CLKDIV = 1, 2, or 3 (CLI divided by setting value) Step 2: CLKDIV = 0 (CLI reprogrammed for no division) Step 3: DIGSTBY = AFESTBY = 0 Step 4: DIGSTBY = AFESTBY = 1
GRAY CODE REGISTERS
Figure 5. Typical System Block Diagram, Master Mode
The AD9898 powers up in slave mode, in which the VD and HD are provided externally from the image processor. In this mode, all AD9898 timing will be synchronized with VD and HD. The H-drivers for H1-H2 and RG are included in the AD9898, allowing these clocks to be directly connected to the CCD. H-drive voltage of up to 3.6 V is supported. An external V-driver is required for the vertical transfer clocks, the sensor gate pulses, and the substrate clock. The AD9898 also includes programmable MSHUT and STROBE outputs, which may be used to trigger mechanical shutter and strobe (flash) circuitry. Figure 6 shows the horizontal and vertical counter dimensions for the AD9898. All internal horizontal and vertical clocking is programmed using these dimensions and is used to specify line and pixel locations.
Table V lists the AD9898 registers requiring gray code values. Below is an example of applying a gray code number for HDLEN using a line length of 1560 pixels: HDLEN = (1560 - 4) = 155610 (See Table XI note about HDLEN.) 155610 = 0x51E The gray code value of 0x51E would be programmed in the 12-bit HDLEN register.
Table V. Gray Code Registers
Register Name HDLEN CLPTOG1 CLPTOG2 HDLASTLEN
Register Type System_Reg(12) System_Reg(15) System_Reg(15 and 16) Mode_Reg(1)
-16-
11-BIT VERTICAL COUNTER = 2048 LINES MAX
Figure 5 shows the typical system block diagram for the AD9898. The CCD output is processed by the AD9898's AFE circuitry, which consists of a CDS, VGA, black level clamp, and A/D converter. The digitized pixel information is sent to the digital image processor chip, which performs the postprocessing and compression. To operate the CCD, all CCD timing parameters are programmed into the AD9898 from the system microprocessor, through the 3-wire serial interface. From the system master clock, CLI, provided by the image processor or external crystal, the AD9898 generates all the CCD's horizontal and vertical clocks and all internal AFE clocks. External synchronization is provided by a SYNC pulse from the microprocessor, which will reset internal counters and resynchronize the VD and HD outputs.
12-BIT HORIZONTALCOUNTER = 4096 PIXELS MAX
REV. 0
AD9898
SERIAL INTERFACE TIMING System Register Serial Interface
All of the internal registers of the AD9898 are accessed through a 3-wire serial interface. The interface consists of a clock (SCK), serial load (SL), and serial data (SDATA). The AD9898 has three different register types that are configured by the 3-wire serial interface. They are control registers, system registers, and mode registers and are described in Table VI.
Table VI. Type of Serial Interface Registers
There are seventeen 32-bit system registers that get accessed sequentially at Address 0x14 beginning with Sys_Reg[0]. When writing to the system registers, SDATA contains the 8-bit address of 0x14, followed by Number Writes N[23:0], followed by the Sys_Reg[31:0] data as shown in Figure 8. The system register map is listed in Table II. There are two options available when writing to the system registers. The choice is automatically determined by the value of the Number Writes N[23:0] word. If Number Writes N[23:0] = 0x000000, the device gets put into a mode where it expects all 17 Sys_Reg[31:0] data-words to be clocked in before SL is asserted high. If the Number Writes N[23:0] is decoded as some number N other than 0x000000, the device expects N number of registers to be programmed where N is equal to the value of Number Writes N[23:0]. For example, if Number Writes N[23:0] = 0x000004, the device would expect data to be provided for Sys_Reg[3:0]. In all cases, the system registers would be written to begin with Sys_Reg[0], no matter what the value of Number Writes N[23:0] is. Note that SL can be brought high or low during access to system registers, as shown in Figure 8.
Mode_A and Mode_B Register Serial Interface
Register Control
Address 0x00 through 0xD6 0x14 0x15 0x16
No. of Registers There is a 24-bit register at each address. Not all addresses are used. See Table I. Seventeen 32-bit system registers at Address 0x14. See Table II. Eight 32-bit Mode_A registers at Address 0x15. See Table III. Eight 32-bit Mode_B registers at Address 0x16. See Table IV.
System Mode_A Mode_B
Control Register Serial Interface
The control register 3-wire interface timing requirements are shown in Figure 7. Control data must be written into the device one address at a time due to the noncontiguous address spacing for the control registers. This requires eight bits of address data followed by 24 bits of configuration data between each active low period of SL for each address. The SL signal must be kept high for at least one full SCK cycle between successive writes to control registers.
There are eight 32-bit Mode_A and eight 32-bit Mode_B registers that get accessed sequentially at Address 0x15 and Address 0x16, respectively. The Mode_A and Mode_B registers get written to exactly as the system registers are. (See the description above.) The mode registers are listed in Tables III and IV. Changing operation between Mode_A and Mode_B is done by setting the 1-bit MODE register (Addr 0x0A). The desired Mode_A (Addr 0x15) or Mode_B (Addr 0x16) data must be programmed into the Mode_A or Mode_B registers before changing the MODE bit.
SDATA
A7
A6
A5
A4
A3
A2
A1
A0
D23
D22
D21
....
D3
D2
D1
D0
t DS
SCK 1
t DH
.... 2 3 4 5 6 7 8 9 10 11 29 30 31 32
t LS
SL 1. SDATA BITS ARE INTERNALLY LATCHED ON THE RISING EDGES OF SCK. 2. SYSTEM UPDATE OF LOADED REGISTERS OCCURS ON SL RISING EDGE. 3. THIS TIMING PATTERN MUST BE WRITTEN FOR EACH REGISTER WRITE WITH SL REMAINING HIGH FOR AT LEAST ONE FULL SCK PERIOD BEFORE ASSERTING SL LOW AGAIN FOR THE NEXT REGISTER WRITE.
t LH
Figure 7. 3-Wire Serial Interface Timing for Control Registers
REV. 0
-17-
AD9898
ADDRESS [7:0] NUMBER WRITES N [23:0] DATA 1 [31:0] DATA 2 [31:0] DATA N [31:0]
N21
N23 N22
N20
D31 D30 D29
D29
D2 D1 D0 D31
N2 N1 N0 D31 D30
D30 D29
A7 A6 A5
A4 A3 A2
A1 A0
N3
D3
D3
8-BIT ADDRESS
NUMBER OF 32-BIT DATA WRITES (N)
DATA 1 [31:0]
DATA 2 [31:0]
D2 D1 D0
SDATA
DATA N [31:0]
SCK
SL
1
1
1
1. ALL SL PULSES ARE IGNORED UNTIL THE LSB OF THE LAST DATA N WORD IS CLOCKED IN. 2. VALID SL PULSE. SL MUST BE ASSERTED HIGH WHEN ALL SDI DATA TRANSMISSIONS HAVE BEEN FINISHED.
Figure 8. System and Mode Register Writes
OPERATION OF VD SYNCHRONOUS TYPE REGISTER WRITES BEGIN AT THE NEXT VD FALLING EDGE.
VD
HD
CLI
PROGRAMMING OF VD SYNCHRONOUS TYPE REGISTERS MUST BE COMPLETED AT LEAST 4 CLI CYCLES BEFORE THE FALLING EDGE OF VD.
Figure 9. VD Synchronous Type Register Writes
VD SYNCHRONOUS AND ASYNCHRONOUS REGISTER OPERATION VD Synchronous Register Operation
There are two types of control registers, VD synchronous and VD asynchronous, as indicated in the address column of Table I. Register writes to synchronous and asynchronous type registers operate differently, as described below. Writes to system, Mode_A, and Mode_B registers occur asynchronously.
Asynchronous Register Operation
For VD synchronous type registers, SDATA data is temporarily stored in a buffer register at the rising edge of SL. This data is held in the buffer register until the next falling edge of VD is applied. Once the next falling edge of VD occurs, the buffered SDATA data is loaded into the serial register and the register operation begins (see Figure 9). All control registers at the following addresses are VD Synchronous type registers--Addr: 0x0A, 0x0B, 0x0C, 0x0D, and 0x0E (see Table I).
For VD asynchronous register writes, SDATA data is stored directly into the serial register at the rising edge of SL. As a result, register operation begins immediately after the rising edge of SL.
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D3 D2 D1 D0
2
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AD9898
ANALOG FRONT END (AFE) DESCRIPTION AND OPERATION PRECISION TIMING HIGH SPEED TIMING GENERATION
The AD9898 AFE signal processing chain is shown in Figure 10. Each processing step is essential to achieving a high quality image from the raw CCD pixel data. Registers for the AD9898 AFE section are listed in Table VII.
DC Restore
To reduce the large dc offset of the CCD output signal, a dc restore circuit is used with an external 0.1 F series coupling capacitor. This restores the dc level of the CCD signal to approximately 1.5 V, which is compatible with the 3 V analog supply of the AD9898.
Correlated Double Sampler
The AD9898 generates flexible high speed timing signals using the Precision Timing core. This core is the foundation for generating the timing used for both the CCD and the AFE signals, including the reset gate RG, the horizontal drivers H1-H2, and the CDS sample clocks. By providing precise control over the horizontal CCD readout and the AFE correlated double sampling, the unique architecture of the AD9898 makes optimizing image quality a routine task for a system designer.
Timing Resolution
To extract the video information and reject low frequency noise, the CDS circuit samples each CCD pixel twice. The timing shown in Figure 12 illustrates how the two internally generated CDS clocks, SHP and SHD, are used to sample the reference level and the data level of the CCD signal, respectively. The placement of the SHP and SHD sampling edges is determined by the setting of the SHPLOC (Addr 0x02) and SHDLOC (Addr 0x02) registers. Placement of these two clock edges is critical to achieving the best performance from the CCD.
Table VII. AFE Registers
The Precision Timing core uses a 1x master clock input (CLI) as a reference. This clock should be the same as the CCD pixel clock frequency. Figure 11 illustrates how the internal timing core divides the master clock period into 48 steps or edge positions. Using a 20 MHz CLI frequency for the AD9898, the edge resolution of the Precision Timing core is 1 ns. A 40 MHz CLI frequency can be applied where the AD9898 will internally divide the CLI frequency by two. Division by one-third and one-fourth is also provided. CLI frequency division is controlled using the CLKDIV (Addr 0xD5) register.
High Speed Clock Programmability
Register Name
Bit Width Register Type
Description
VGAGAIN 10 REFBLACK 6 AFESTBY 1
Control (Addr 0x0E) VGA Gain Control (Addr 0x04) Blk Clamp Level Control (Addr 0x05) AFE Standby
Figure 13 shows how the high speed clocks RG, H1-H2, SHP, and SHD are generated. The RG pulse has a fixed rising edge and a programmable falling edge. The horizontal clock H1 has a programmable rising and a fixed falling edge occurring at H1POSLOC + 24 steps. The H2 clock is always the inverse of H1. Table VIII summarizes the high speed timing registers and the parameters for the high speed clocks. Each register is six bits wide with the 2 MSB used to select the quadrant region as outlined in Table VIII. Figure 13 shows the range and default locations of the high speed clock signals.
1.0 F REFB DC RESTORE 1.5V SHP SHD 6dB TO 40dB 0.1 F CCDIN CDS VGA 1.0V
1.0 F REFT 2.0V
AD9898
INTERNAL VREF 2V FULL SCALE OUTPUT DATA LATCH DOUT PHASE
ADC
10 DOUT
10 VGA GAIN REGISTER 8-BIT DAC
OPTICAL BLACK CLAMP CLPOB DIGITAL FILTER 6
SHP
DOUT SHD PHASE
CLPOB CLAMP LEVEL REGISTER
PRECISION TIMING GENERATION
V-H TIMING GENERATION
Figure 10. AFE Block Diagram
REV. 0
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AD9898
H-Driver and RG Outputs
In addition to the programmable timing positions, the AD9898 features on-chip output drivers for the RG and H1-H2 outputs. They are sufficiently powerful to directly drive the CCD inputs. The H-driver current can be adjusted for optimum rise/fall time into a particular load by using the H1DRV and H2DRV registers (Addr 0x04). The RG drive current is adjustable using the RGDRV register (Addr 0x04). The H1DRV and H2DRV register is adjustable in 4.3 mA increments. The RGDRV register is adjustable in 2.15 mA increments. All DRV registers have a setting of 0 equal to OFF or three-state, and the maximum setting of 7.
POSITION P[0] P[12]
As shown in Figure 13, the H2 output is the inverse of H1. The internal propagation delay resulting from the signal inversion is less than 1 ns, which is significantly less than the typical rise time driving the CCD load. This results in an H1/H2 crossover voltage of approximately 50% of the output swing. The crossover voltage is not programmable.
Digital Data Outputs
The AD9898 DOUT[9:0] and DCLK phases are independently programmable using the DOUTPHASE register (Addr 0x02) and DCLKPHASE register (Addr 0x02) (see Figure 15).
P[24]
P[36]
P[48] = P[0]
CLI
t CLIDLY
1 PIXEL PERIOD
1. PIXEL CLOCK PERIOD IS DIVIDED INTO 48 POSITIONS, PROVIDING FINE EDGE RESOLUTION FOR HIGH SPEED CLOCKS. 2. THERE IS A FIXED DELAY FROM THE CLI INPUT TO THE INTERNAL PIXEL PERIOD POSITIONS (t CLIDLY = 6 ns TYP).
Figure 11. High Speed Clock Resolution from CLI Master Clock Input
3 CCD SIGNAL 4
cds (INTERNAL)
1 RG
2
5 H1
6
H2
PROGRAMMABLE CLOCK POSITIONS 1. RG RISING EDGE (FIXED EDGE AT 000000). 2. RG FALLING EDGE (RGNEGLOC (ADDR 0x03)). 3. SHP SAMPLE LOCATION (SHPLOC (ADDR 0x02)). 4. SHD SAMPLE LOCATION (SHDLOC (ADDR 0x02)). 5. H1 RISING EDGE LOCATION (H1POSLOC (ADDR 0x03)) 6. H1 NEGATIVE EDGE LOCATION (FIXED AT (H1POSLOC + 24 STEPS)). 7. H2 IS ALWAYS THE INVERSE OF H1.
Figure 12. High Speed Clock Programmable Locations
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AD9898
Table VIII. RG, H1, SHP, SHD, DCLK, and DOUTPHASE Timing Parameters
Register Name RGNEGLOC H1POSLOC SHPLOC SHDLOC DOUTPHASE DCLKPHASE
Bit Width 6 6 6 6 6 6
Register Type Control (Addr 0x03) Control (Addr 0x03) Control (Addr 0x02) Control (Addr 0x02) Control (Addr 0x02) Control (Addr 0x02)
Range 0-47 Edge Location 0-47 Edge Location 0-47 Edge Location 0-47 Edge Location 0-47 Edge Location 0-47 Edge Location
Description Falling Edge Location for RG Positive Edge Location for H1 Sample Location for SHP Sample Location for SHD Phase Location of Data Output [9:0] Positive Edge of DCLK 1
The 2 MSB are used to select the quadrant.
Table IX. Precision Timing Edge Locations for RG, H1, SHP, SHD, DCLK, and DOUTPHASE
RG Rising Edge Signal Name RG Quadrant I II III IV (Not Programmable) Fixed at 000000 Fixed at 000000 Fixed at 000000 Fixed at 000000 H1 Rising Edge Signal Name H1 Quadrant I II III IV H1POSLOC 000000 to 001011 010000 to 011011 100000 to 101011 110000 to 111011 cds Rising Edge Signal Name cds Quadrant I II III IV SHPLOC 000000 to 001011 010000 to 011011 100000 to 101011 110000 to 111011 Quadrant Range P[0] to P[11] P[12] to P[23] P[24] to P[35] P[36] to P[47] Quadrant Range P[0] to P[11] P[12] to P[23] P[24] to P[35] P[36] to P[47]
RG Falling Edge RGNEGLOC 000000 to 001011 010000 to 011011 100000 to 101011 110000 to 111011 Quadrant Range P[0] to P[11] P[12] to P[23] P[24] to P[35] P[36] to P[47] H1 Falling Edge (Not Programmable) H1POSLOC + 24 Steps H1POSLOC + 24 Steps H1POSLOC + 24 Steps H1POSLOC + 24 Steps cds Falling Edge SHDLOC 000000 to 001011 010000 to 011011 100000 to 101011 110000 to 111011 Quadrant Range P[0] to P[11] P[12] to P[23] P[24] to P[35] P[36] to P[47]
Data Output[9:0] Rising Edge Signal Name Data Output[9:0] Quadrant I II III IV DOUTPHASE 000000 to 001011 010000 to 011011 100000 to 101011 110000 to 111011 Quadrant Range P[0] to P[11] P[12] to P[23] P[24] to P[35] P[36] to P[47]
Data Output[9:0] Falling Edge (Not Programmable) DOUTPHASE + 24 Steps DOUTPHASE + 24 Steps DOUTPHASE + 24 Steps DOUTPHASE + 24 Steps DCLKPHASE Falling Edge P[26] P[36] P[06] P[16]
Signal Name DCLK1
DCLKPHASE Value 00 01 10 11
DCLKPHASE Rising Edge P[6] P[16] P[26] P[36]
REV. 0
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AD9898
POSITION PIXEL PERIOD RGr[0] RG RGf[12] P[0] P[12] P[24] P[36] P[48] = P[0]
Hr[0] H1
Hf[24]
cds (INTERNAL)
t S1
SHP[20] CCD SIGNAL SHD[40]
1. ALL SIGNAL EDGES ARE FULLY PROGRAMMABLE TO ANY OF THE 48 POSITIONS WITHIN ONE PIXEL PERIOD. 2. DEFAULT POSITIONS FOR EACH SIGNAL ARE SHOWN.
Figure 13. High Speed Clock Default and Programmable Locations
t RISE
H1 H2
t PD < t RISE
H1 FIXED CROSSOVER VOLTAGE
t PD
H2
Figure 14. H-Clock Inverse Phase Relationship
P[0] PIXEL PERIOD
P[12]
P[24]
P[36]
P[48] = P[0]
DCLK1
t OD
DOUT
1. DCLK1 PHASE IS ADJUSTED BY SETTING THE DCLKPHASE REGISTER (ADDR 0x02). 2. DOUT PHASE CAN BE ADJUSTED BY SETTING THE DOUTPHASE REGISTER (ADDR 0x02).
Figure 15. Digital Output Phase Adjustment
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AD9898
EXTERNAL SYNCHRONIZATION (MASTER MODE) Table X. External Synchronization (Master Mode)
External synchronization can be used to synchronize the VD and HD signal by applying an external pulse on the SYNC/ VGATE pin (Pin 45) for master mode operation. The SYNC/ VGATE pin is configured as an external SYNC input for master mode operation by setting the SLAVE_MODE register (Addr 0xD6) = 0. (The AD9898 defaults to slave mode at power-up.) SYNCCNT (Addr 0x0A) and SYNCPOL (Addr 0x01) are the only two registers used for configuring the AD9898 for external synchronization. The SYNCPOL is a 1-bit register used for configuring the SYNC input as either active low or active high. The AD9898 defaults to active low at power-up. The function of the SYNCCNT register is described in Table X. Figures 16 and 17 provide two examples of external synchronization with SYNCPOL = 0.
SYNCCNT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
External Synchronization Options Disable External Synchronization VD Sync at every SYNC Pulse VD Sync after Second Applied SYNC Pulse VD Sync after Third Applied SYNC Pulse VD Sync after Fourth Applied SYNC Pulse VD Sync after Fifth Applied SYNC Pulse VD Sync after Sixth Applied SYNC Pulse VD Sync after Seventh Applied SYNC Pulse VD Sync after Eighth Applied SYNC Pulse VD Sync after Ninth Applied SYNC Pulse VD Sync after Tenth Applied SYNC Pulse VD Sync after Eleventh Applied SYNC Pulse VD Sync after Twelfth Applied SYNC Pulse VD Sync after Thirteenth Applied SYNC Pulse VD Sync after Fourteenth Applied SYNC Pulse VD Sync after First Applied SYNC Pulse Only
4 CLI
4 CLI
4 CLI
VD
SYNC 2 CLIMIN CHANGE TO MODE B SERIAL WRITES
OPERATION MODE
MODE A
MODE B
Figure 16. Example of Synchronization with SYNCPOL = 0 and SYNCCNT = 1
4 CLI
4 CLI
4 CLI
VD
SYNC 2 CLIMIN
Figure 17. Example of Synchronization with SYNCPOL = 0 and SYNCCNT = 3
REV. 0
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AD9898
HORIZONTAL AND VERTICAL SYNCHRONOUS TIMING Special Note about the HDLEN Register
The HD and VD output pulses are programmable using the registers listed in Table XI. The HD output is asserted low at the start of the horizontal line shift. The VD output is asserted low at the start of each line. As shown in Figure 18, the 11-bit VD counter is used to count the number of lines set by the VDLEN register. The 12-bit HD counter is used to count the number of pixels in each line set by the HDLEN register. For example, if the CCD array size is 2000 lines by 2100 pixels per line, VDLEN = 2000 and HDLEN = 0xC28. The HLEN register sets the HL counter that is used as a reference for the rising edge of the HD pulse.
The 12-bit HD counter value must be programmed using a gray code number. There is also a 4-clock cycle setup period that must be considered when determining the HDLEN register value, as shown in Figure 18. As a result of the 4-clock cycle setup period, the value of HDLEN is always equal to the actual number of pixels per line minus four. For example, if there are 2100 pixels per line, HDLEN equals (2100 - 4) = 2096. The gray code value of 2096 is 0xC28, which is what would be programmed in the HDLEN register.
Table XI. HD and VD Registers
Register Name HDLEN HLEN HDRISE HDLASTLEN* VDLEN VDRISE
Bit Width 12 10 10 12 11 4
Register Type Sys_Reg(12) Sys_Reg(12) Sys_Reg(16) Mode_Reg(1) Mode_Reg(1) Sys_Reg(16)
Reference Counter
Range 0-4095 Pixels 0-1023 Pixels 0-1023 Pixels 0-4095 Pixels 0-2047 Lines 0-15 Lines
Description 12-Bit Gray Code Counter Value 10-Bit HL Counter Value HD Rise Position HD Last Line Length VD Counter Value VD Rise Position
HL HD VD
*Register value must be a gray code number. (See Gray Code Registers section.)
VDLEN 11-BIT VD COUNTER 000 001 002 N 2048
HDLEN 12-BIT GRAY COUNTER + SETUP HLEN 10-BIT HL COUNTER
SETUP
HDLASTLEN
VD
2
HD
1 LINE LENGTH = HDLEN + 4
1. THE SETUP DELAY IS 4 CLI CYCLES. THE ACTUAL LENGTH OF ONE LINE IS 4 MORE CYCLES THAN THE VALUE SET IN HDLEN AND HDLASTLEN DUE TO SETUP DELAY. 2. VDRISE REFERENCES THE 11-BIT VD COUNTER. 3. HDRISE REFERENCES THE 10-BIT HL COUNTER. PROGRAMMABLE CLOCK POSITIONS 1. HDRISE (SYS_REG(16)) 2. VDRISE (SYS_REG(16))
Figure 18. VD and HD Horizontal Timing
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AD9898
Table XII. CLPOB Registers
Register Name
Bit Width Register Type Control (0x01) Control(0x01)
Reference Counter Range
Description
CLP_CONT 1 CLP_MODE 1
CLPTOG1 CLPTOG2 CLPEN0 CLPEN1 CLPEN2 CLPEN3 CLPEN4
12 12 1 1 1 1 1
Sys_Reg(15) HD Sys_Reg(15 and 16) HD Mode_Reg(2) Mode_Reg(2) Mode_Reg(2) Mode_Reg(2) Mode_Reg(2)
CLPOB Control (0 = CLPOB Off, 1 = CLPOB On) CLPOB CCD Region Control (0 = Enable CLPENx Register Settings, 1 = Disable CLPENx Register Settings) 0-4095 Pixel Locations CLPOB Toggle Position 1 (Gray Code Number) 0-4095 Pixel Locations CLPOB Toggle Position 2 (Gray Code Number) CLPOB Control for CCD Region 0 (0 = CLPOB Disabled, 1 = CLPOB Enabled) CLPOB Control for CCD Region 1 (0 = CLPOB Disabled, 1 = CLPOB Enabled) CLPOB Control for CCD Region 2 (0 = CLPOB Disabled, 1 = CLPOB Enabled) CLPOB Control for CCD Region 3 (0 = CLPOB Disabled, 1 = CLPOB Enabled) CLPOB Control for CCD Region 4 (0 = CLPOB Disabled, 1 = CLPOB Enabled)
VD
HD
12-BIT GRAY COUNTER + SETUP
CLPOB PROGRAMMABLE CLOCK POSITIONS 1. CLPTOG1 (SYS_REG(15)) 2. CLPTOG2 (SYS_REG(15 AND 16))
1
2
Figure 19. Location of CLPOB Using CLPTOG1 and CLPTOG2 Registers
HORIZONTAL CLAMPING AND BLANKING
The AD9898's horizontal clamping and blanking pulses are programmable to suit a variety of applications. Similar to vertical timing generation, individual sequences are defined for each signal and are then organized into multiple regions during image readout. This allows the dark pixel clamping and blanking patterns to be changed at each stage of the readout to accommodate different image transfer timing and high speed line shifts.
Controlling CLPOB Clamp Pulse Timing
Figure 21 shows that no CLPOB pulse will be applied when the last HD length set by HDLASTLEN is longer than the regular HD length. Note that the CLPOB pulse is applied in the last line only when HDLASTLEN = HDLEN.
HD
CLPOB LAST LINE
The AFE horizontal CLPOB pulse is generated based on the 12-bit gray code counter. Once the length of the 12-bit gray code counter is set using the HDLEN register (Sys_Reg(12)), CLPTOG1 and CLPTOG2 registers (Sys_Reg(15 and16)) can be used to place the CLPOB pulse location, as shown in Figure 19. Table XII lists all CLPOB registers that are used to configure and control the placement and output of the CLPOB pulse. The length of the last HD line is set using the HDLASTLEN register (Sys_Reg(1)). Figure 20 shows that no CLPOB pulse will be asserted when the last HD length set by HDLASTLEN is shorter than the regular HD length set by HDLEN. REV. 0 -25-
Figure 20. Last HD Shorter Than Regular HD
HD
CLPOB LAST LINE
Figure 21. Last HD Longer Than Regular HD
AD9898
Controlling CLPOB Clamp Pulse Outputs Table XIII. SCP and CLPEN
The registers in Table XII are used for programming the CLPOB pulse, which will be disabled in all CCD regions by setting CLPCNT = 0. The CLPTOGx (x = 0, 1) are used to set the CLPOB toggle positions. The CLPENx (x = 0, 1, 2, 3, and 4) are used to enable or disable the CLPOB pulse separately in each CCD region when CLPMODE = 0. The CLPEN registers have no effect if CLPMODE = 1. In this case, the CLPOB pulse will be asserted in all CCD regions, regardless of the value set in the CLPENx registers. Figure 22 shows an example of the CLPOB pulse being disabled in CCD Regions 1 and 3 by setting CLPEN1 = 1 and CLPEN3 = 1. Note that the CLPOB pulse remains disabled in the first line of the following CCD region.
SCP[4:1] SCP0* SCP1 SCP2 SCP3 SCP4
CLPEN[4:0] CLPEN0 CLPEN1 CLPEN2 CLPEN3 CLPEN4
*SCP0 is not a programmable register and therefore is not listed in the register map tables. SCP0 is a fixed sequence and always starts at the falling edge of VD. Although this register is not programmable, the CLPEN0 register is still used to enable or disable the CLPOB pulse for the SCP0 region.
VD
HD
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLPOB
CLPMASK (INTERNAL) 1 2 3
A 4 5
B
PROGRAMMING POSITIONS 1. SCP0 = 0 (FIXED), CLPEN0 = 1 2. SCP1 = 3, CLPEN1 = 0 3. SCP2 = 4, CLPEN2 = 1 4. SCP3 = 5, CLPEN3 = 0 5. SCP4 = 1, CLPEN4 = 1 NOTE THE INTERNAL CLPMASK SIGNAL EXTENDS ONE EXTRA HD CYCLE FROM THE TIME WHEN THE CLPMASK PERIOD CHANGES FROM LOW TO HIGH. AS A RESULT, ONE ADDITIONAL CLPOB PULSE IS MASKED, AS SHOWN AT POSITIONS A AND B.
Figure 22. CLPOB Outputs with CLPMODE = 0
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AD9898
H1 AND H2 BLANKING Selective Positioning for Two H1 and H2 Outputs
The AD9898 provides three options for controlling the period where H1 and H2 pulses get blanked. These options are normal H blanking, selective positioning for 2 H1 and H2 outputs, and extended blanking. In all cases, HBLKMASK is used to set the polarity of H1 during the blanking period. Table XIV describes the registers used to control H blanking.
Normal H Blanking
For selective positioning operation, HPULSECNT = 1 and HBLKMASK = 0 or 1. In this mode, two H1 pulses are output during the blanking period. The location of these two pulses are set using the HBLKHPOS register, as shown in Figure 24.
Extended Blanking
For normal H blanking operation, HPULSECNT = 0 and BLKMASK = 0 or 1. The HBLKHPOS register is not used in this mode. Figure 23 shows one example where HBLKMASK = 0. As seen in Figure 23, H1 and H2 are blanked while HD is Low.
Extended blanking is enabled by setting HBLKEXT = 1. The HBLKEXT register uses the 9-bit BL counter to suspend operation of the HD and HL counters. This delays the blanking period by the length set in the BLLEN register as shown in Figure 25.
Table XIV. H1 Blanking Registers
Register Name HBLKMASK HPULSECNT HBLKEXT H1BLKRETIME HBLKHPOS
Bit Width 1 1 1 1 10
Register Type Control (0x01) Control (0x0A) Control (0x0A) Control (0x03) Sys_Reg(11)
Description Masking Polarity for H1 during Blanking Period1 (0 = Low, 1 = High) H Pulse Control during Blanking Period (0 = No Output during Blanking, 1 = Output during Blanking) H Pulse Blanking Extend Control2 (0 = Extended Blanking Disabled, 1 = Extended Blanking Enabled) Retimes the H1 HBLK to Internal Clock (0 = Retiming Disabled, 1 = Retiming Enabled) H1 Pulse ON Position during Blanking Period
NOTES 1 The polarity of H2 is always the opposite polarity of the H1 polarity. 2 The HBLKEXT extend control extends the blanking period by the number of counts set in the BLLEN register for the 9-bit BL counter.
HD HDRISE HBLK (INTERNAL) 1
H1
H2
RG
1. THE RISING EDGE OF HBLK IS ALWAYS THE SAME AS HDRISE.
Figure 23. Normal H-Blanking Operation HBLKMASK = 0, HPULSECNT = 0, HBLKHPOS = xxx
REV. 0
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AD9898
HD
HBLK (INTERNAL)
H12 (INTERNAL)
RG
H1 THE H2 POLARITY IS OPPOSITE THE POLARITY OF H1.
Figure 24. Selective H-Blanking Operation HBLKMASK = 0, HPULSECNT = 1, HBLKHPOS = 003
BLLEN 9-BIT BL COUNTER
VD
HD
1
H1
2
CLPOB
3
4
1. POSITIONS 1, 2, 3, AND 4 ARE DELAYED BY THE VALUE OF THE BL COUNTER. 2. VSG1, VSG2, V1-V4, AND SUBCK PULSES ARE NOT DELAYED BY THE BL COUNTER.
Figure 25. VD, HD, and H1 Extended Blanking Operation HBLKEXT = 1
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AD9898
VGATE MASKING OF V1-V4 AND CLPOB OUTPUTS
During slave mode operation, the SYNC/VGATE, Pin 45, is configured as an input for an external VGATE signal. While operating in this mode, the external VGATE signal can be used to mask the V1-V4 and CLPOB outputs. There are two options available for masking the V1-V4 and CLPOB outputs. The selection is made by setting the MSHUT/VGATE_EN register located at Control Addr 0x01. Examples of these two options are shown in Figures 26 and 27.
Figure 26 shows an example of MSHUT/VGATE_EN = 0. In this example, the VGATE signal is internally latched on the falling edge of HD, resulting in the V1-V4 and CLPOB outputs being masked when the internally latched VGATE signal is High. Figure 27 shows an example when MSHUT/VGATE_EN = 1. In this example, the preprogrammed MSHUT signal blocks the VGATE input from masking V1-V4 and CLPOB outputs while MSHUT is Low. The internally latched VGATE signal will only mask V1-V4 and CLPOB when MSHUT is High while operating in this mode.
VD
HD
VGATE (PIN 45)
VGATE (INTERNAL)
V1-V4
CLPOB V1-V4 AND CLPOB MASKED V1-V4 AND CLPOB MASKED
Figure 26. Example of VGATE Input Masking V1-V4 and CLPOB Outputs with MSHUT/VGATE_EN = 0
VD
HD
VGATE (PIN 45)
VGATE (INTERNAL)
MSHUT
V1-V4
CLPOB V1-V4 AND CLPOB MASKED
Figure 27. Example of VGATE Input Masking V1-V4 and CLPOB Outputs with MSHUT/VGATE_EN = 1
REV. 0
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AD9898
VERTICAL TIMING GENERATION
The AD9898 provides a very flexible solution for generating vertical CCD timing and can support multiple CCDs and different system architectures. The 4-phase vertical transfer clocks V1-V4 are used to shift each line of pixels into the horizontal output register of the CCD. The AD9898 vertical outputs can be individually programmed into four different vertical pulse patterns identified as VTP0, VTP1, VTP2, and VTP3. Each vertical pulse pattern is a unique set of preconfigured V1-V4 sequences. Once the vertical patterns have been configured using the registers in Table XVII, pointer registers are used to select which region of the CCD a particular vertical pattern is output in. The pointer registers are described in Table XV. Up to five unique CCD regions may be specified. The readout of the entire field is constructed by combining one or more of the individual regions sequentially. With up to five region areas available, different steps of the readout, such as high speed line shifts and vertical image transfer, can be supported.
Creating Vertical Sequences
Step 2 Create the Individual Vertical Sequences (See Figure 29)
The individual vertical sequences are created by assigning pulse repetitions to patterns VTP0, VTP1, VTP2, and VTP3, using VTPREPx registers in Table XVI. The number of repetitions (VTPREPx) determines the number of pulse repetitions desired within a single line. Programming 1 for VTPREPx gives a single pulse, while setting it to 0 will provide a fixed dc output based on the start polarity value. Figure 29 shows an example of a VTPx sequence of two VTPx patterns made by setting VTPREPx = 2.
Step 3 Output Vertical Sequences into CCD Regions (See Figure 30)
Figures 28, 29, and 30 provide an overview of how the vertical timing is generated in four basic steps.
Step 1 Create the Individual Pulses for Patterns VTP0, VTP1, VTP2, and VTP3 (See Figure 28)
The AD9898 arranges individual sequences into CCD regions through the use of sequence pointers (VTPSEQPTRx) and vertical transfer pattern select (VTPSELx) registers, as described in Table XVI. The VTPSEQPTRx registers are used to point to a desired VTPSELx register whose value determines what VTPx pattern will be output on the V1-V4 pins. For example, if VTPSEQPTR0 = 1 and VTPSEL1 = 2, the VTP2 pulse pattern would output while operating in Region 0 of the CCD.
Step 4 Combining CCD Regions (See Figure 30)
The entire field readout can be built by combining multiple regions by using mode registers SCP0, SCP1, SCP2, SCP3, and SCP4. The individual CCD regions are combined into a complete field readout using the sequence change position (SCPx) pointers as described in Table XVII. Figure 30 shows how each field is divided into multiple regions which allows the user to change vertical timing during various stages of the image readout. The boundaries of each region are defined by the sequence change position (SCP). Each SCP is an 8-bit value representing the line number boundary region. A total of four SCPs allow up to five different regions in the field to be defined. The first SCP0 is always hard coded to line zero, and the remaining four SCPs are register programmable.
The registers shown in Table XV are used to generate the individual vertical timing pulses, as shown in Figure 28. The VTPLENx determines the number of pixels between pulse repetitions. The start polarity (VxSTARTPOLx) sets the starting polarity of the vertical sequence and can be programmed high or low. The first toggle position (VxTOG1POSx) and second toggle position (VxTOG2POSx) are the pixel locations within the line where the pulse transitions.
0
50
100
150
200
250
300
350
400
HD
V1
1
2
3
V2
4
5
6
V3
7
8
9
V4
10
11 VTPLENx [8:0] = 210
12
PROGRAMMABLE CLOCK POSITIONS 1. V1STARTPOLx = 0 2. V1TOG1x[8:0] = 50 3. V1TOG2x[8:0] = 130 4. V2STARTPOLx = 1 5. V2TOG1x[8:0] = 30 6. V2TOG2x[8:0] = 150 7. V3STARTPOLx = 1 8. V3TOG1x[8:0] = 110 9. V3TOG2x[8:0] = 180 10. V4STARTPOLx = 0 11. V4TOG1x[8:0] = 20 12. V4TOG2x[8:0] = 160
Figure 28. Step 1: Create Individual Vertical Pulses for VTP0, VTP1, VTP2, and VTP3 Patterns
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0 50 100 150 200 250 300 350 400 HD
V1
1
2
3
V2
4
5
6
V3
7
8
9
V4
10
11
12
VTPLENx [8:0] = 210
Figure 29. Step 2: Create Individual Sequences for V1-V4 Outputs by Assigning Pulse Repetitions to VTP0, VTP1, VTP2, and VTP3 Patterns. This Example Shows VTPREPx = 2.
CCD REGION0 SCP0 (FIXED AT LINE 0)
VERTICAL TRANSFER PULSES SCP1 [7:0] CCD REGION1
V1 V2 V3 V4 V1 V2 V3 V4
VTP0
V1 V2 V3 V4 V1 V2 V3 V4
VTP1 CCD REGION2
SCP2 [7:0]
VTP2
VTP3 SCP3 [7:0] CCD REGION3
SCP4 [7:0] CCD REGION4
SCP 0 REGION 0 (FIXED AT LINE 0) VD
SCP 1 REGION 1 (LINE 4)
SCP 2 REGION 2 (LINE 7)
SCP 4 REGION 4 (LINE (N + 7))
HD
V1
V2
V3
V4
VTP0 VTPREP0 = 2
VTP0 VTPREP0 = 1
VTP2 VTPREP2 = 2
VTP1 VTPREP1 = 1
Figure 30. Steps 3 and 4: Example of Building an Entire Field Readout by Assigning Sequences to Multiple CCD Regions
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Table XV. V1-V4 Registers to Configure V1-V4 Pulse for Each VTP Pattern
Register Name VTPLEN0 V1STARTPOL0 V2STARTPOL0 V3STARTPOL0 V4STARTPOL0 V1TOG1POS0 V1TOG2POS0 V2TOG1POS0 V2TOG2POS0 V3TOG1POS0 V3TOG2POS0 V4TOG1POS0 V4TOG2POS0 VTPLEN1 V1STARTPOL1 V2STARTPOL1 V3STARTPOL1 V4STARTPOL1 V1TOG1POS1 V1TOG2POS1 V2TOG1POS1 V2TOG2POS1 V3TOG1POS1 V3TOG2POS1 V4TOG1POS1 V4TOG2POS1 VTPLEN2 V1STARTPOL2 V2STARTPOL2 V3STARTPOL2 V4STARTPOL2 V1TOG1POS2 V1TOG2POS2 V2TOG1POS2 V2TOG2POS2 V3TOG1POS2 V3TOG2POS2 V4TOG1POS2 V4TOG2POS2 VTPLEN3 V1STARTPOL3 V2STARTPOL3 V3STARTPOL3 V4STARTPOL3 V1TOG1POS3 V1TOG2POS3 V2TOG1POS3 V2TOG2POS3 V3TOG1POS3 V3TOG2POS3 V4TOG1POS3 V4TOG2POS3 Bit Width 9 1 1 1 1 9 9 9 9 9 9 9 9 9 1 1 1 1 9 9 9 9 9 9 9 9 9 1 1 1 1 9 9 9 9 9 9 9 9 9 1 1 1 1 9 9 9 9 9 9 9 9 Register Type Sys_Reg(1) Sys_Reg(1) Sys_Reg(1) Sys_Reg(1) Sys_Reg(1) Sys_Reg(1) Sys_Reg(1) Sys_Reg(1 and 2) Sys_Reg(2) Sys_Reg(2) Sys_Reg(2 and 3) Sys_Reg(3) Sys_Reg(3) Sys_Reg(3) Sys_Reg(3) Sys_Reg(3) Sys_Reg(4) Sys_Reg(4) Sys_Reg(4) Sys_Reg(4) Sys_Reg(4) Sys_Reg(4 and 5) Sys_Reg(5) Sys_Reg(5) Sys_Reg(5 and 6) Sys_Reg(6) Sys_Reg(6) Sys_Reg(6) Sys_Reg(6) Sys_Reg(6) Sys_Reg(6) Sys_Reg(6) Sys_Reg(7) Sys_Reg(7) Sys_Reg(7) Sys_Reg(7 and 8) Sys_Reg(8) Sys_Reg(8) Sys_Reg(8) Sys_Reg(9) Sys_Reg(9) Sys_Reg(9) Sys_Reg(9) Sys_Reg(9) Sys_Reg(9) Sys_Reg(9) Sys_Reg(9 and 10) Sys_Reg(10) Sys_Reg(10) Sys_Reg(10 and 11) Sys_Reg(11) Sys_Reg(11) Reference Counter V Counter Range 0-511 High/Low High/Low High/Low High/Low 0-511 0-511 0-511 0-511 0-511 0-511 0-511 0-511 0-512 High/Low High/Low High/Low High/Low 0-511 0-511 0-511 0-511 0-511 0-511 0-511 0-511 0-512 High/Low High/Low High/Low High/Low 0-511 0-511 0-511 0-511 0-511 0-511 0-511 0-511 0-512 High/Low High/Low High/Low High/Low 0-511 0-511 0-511 0-511 0-511 0-511 0-511 0-511 Description Length between Repetitions V1 Starting Polarity for VTP0 (0 = LO, 1 = HI) V2 Starting Polarity for VTP0 (0 = LO, 1 = HI) V3 Starting Polarity for VTP0 (0 = LO, 1 = HI) V4 Starting Polarity for VTP0 (0 = LO, 1 = HI) V1 Toggle Position 1 for VTP0 V1 Toggle Position 2 for VTP0 V2 Toggle Position 1 for VTP0 V2 Toggle Position 2 for VTP0 V3 Toggle Position 1 for VTP0 V3 Toggle Position 2 for VTP0 V4 Toggle Position 1 for VTP0 V4 Toggle Position 2 for VTP0 Length between Repetitions V1 Starting Polarity for VTP1 (0 = LO, 1 = HI) V2 Starting Polarity for VTP1 (0 = LO, 1 = HI) V3 Starting Polarity for VTP1 (0 = LO, 1 = HI) V4 Starting Polarity for VTP1 (0 = LO, 1 = HI) V1 Toggle Position 1 for VTP1 V1 Toggle Position 2 for VTP1 V2 Toggle Position 1 for VTP1 V2 Toggle Position 2 for VTP1 V3 Toggle Position 1 for VTP1 V3 Toggle Position 2 for VTP1 V4 Toggle Position 1 for VTP1 V4 Toggle Position 2 for VTP1 Length between Repetitions V1 Starting Polarity for VTP2 (0 = LO, 1 = HI) V2 Starting Polarity for VTP2 (0 = LO, 1 = HI) V3 Starting Polarity for VTP2 (0 = LO, 1 = HI) V4 Starting Polarity for VTP2 (0 = LO, 1 = HI) V1 Toggle Position 1 for VTP2 V1 Toggle Position 2 for VTP2 V2 Toggle Position 1 for VTP2 V2 Toggle Position 2 for VTP2 V3 Toggle Position 1 for VTP2 V3 Toggle Position 2 for VTP2 V4 Toggle Position 1 for VTP2 V4 Toggle Position 2 for VTP2 Length between Repetitions V1 Starting Polarity for VTP3 (0 = LO, 1 = HI) V1 Starting Polarity for VTP3 (0 = LO, 1 = HI) V1 Starting Polarity for VTP3 (0 = LO, 1 = HI) V1 Starting Polarity for VTP3 (0 = LO, 1 = HI) V1 Toggle Position 1 for VTP3 V1 Toggle Position 2 for VTP3 V2 Toggle Position 1 for VTP3 V2 Toggle Position 2 for VTP3 V3 Toggle Position 1 for VTP3 V3 Toggle Position 2 for VTP3 V4 Toggle Position 1 for VTP3 V4 Toggle Position 2 for VTP3 VTP Pattern
V Counter V Counter V Counter V Counter V Counter V Counter V Counter V Counter V Counter
V T P 0
V Counter V Counter V Counter V Counter V Counter V Counter V Counter V Counter V Counter
V T P 1
V Counter V Counter V Counter V Counter V Counter V Counter V Counter V Counter V Counter
V T P 2
V Counter V Counter V Counter V Counter V Counter V Counter V Counter V Counter
V T P 3
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Table XVI. Mode_A and Mode_B Registers for VTPx Selection
Register Name VTPSEQPTR0*
Bit Width 3
Register Type Mode_Reg(2)
Range
Description Vertical Transfer Pulse Pointer Used in CCD Region 0 (0 = VTPSEL0, 1 = VTPSEL1, 2 = VTPSEL2, 3 = VTPSEL3 4 = VTPSEL0 for EVEN Line and VTPSEL1 for ODD Line 5 = VTPSEL2 for EVEN Line and VTPSEL3 for ODD Line) Vertical Transfer Pulse Pointer Used in CCD Region 1 (0 = VTPSEL0, 1 = VTPSEL1, 2 = VTPSEL2, 3 = VTPSEL3 4 = VTPSEL0 for EVEN Line and VTPSEL1 for ODD Line 5 = VTPSEL2 for EVEN Line and VTPSEL3 for ODD Line) Vertical Transfer Pulse Pointer Used in CCD Region 2 (0 = VTPSEL0, 1 = VTPSEL1, 2 = VTPSEL2, 3 = VTPSEL3 4 = VTPSEL0 for EVEN Line and VTPSEL1 for ODD Line 5 = VTPSEL2 for EVEN Line and VTPSEL3 for ODD Line) Vertical Transfer Pulse Pointer Used in CCD Region 3 (0 = VTPSEL0, 1 = VTPSEL1, 2 = VTPSEL2, 3 = VTPSEL3 4 = VTPSEL0 for EVEN Line and VTPSEL1 for ODD Line 5 = VTPSEL2 for EVEN Line and VTPSEL3 for ODD Line) Vertical Transfer Pulse Pointer Used in CCD Region 4 (0 = VTPSEL0, 1 = VTPSEL1, 2 = VTPSEL2, 3 = VTPSEL3 4 = VTPSEL0 for EVEN Line and VTPSEL1 for ODD Line 5 = VTPSEL2 for EVEN Line and VTPSEL3 for ODD Line) (0 = VTP0, 1 = VTP1, 2 = VTP2, 3 = VTP3) (0 = VTP0, 1 = VTP1, 2 = VTP2, 3 = VTP3) (0 = VTP0, 1 = VTP1, 2 = VTP2, 3 = VTP3) (0 = VTP0, 1 = VTP1, 2 = VTP2, 3 = VTP3) Number of VTP0 Pulse Repetitions within a Line Number of VTP1 Pulse Repetitions within a Line Number of VTP2 Pulse Repetitions within a Line Number of VTP3 Pulse Repetitions within a Line
VTPSEQPTR1*
3
Mode_Reg(2)
VTPSEQPTR2*
3
Mode_Reg(2)
VTPSEQPTR3*
3
Mode_Reg(2)
VTPSEQPTR4*
3
Mode_Reg(2)
VTPSEL0 VTPSEL1 VTPSEL2 VTPSEL3 VTPREP0 VTPREP1 VTPREP2 VTPREP3
2 2 2 2 3 3 3 3
Mode_Reg(3) Mode_Reg(3) Mode_Reg(3) Mode_Reg(3) Mode_Reg(3) Mode_Reg(4) Mode_Reg(4) Mode_Reg(4)
0-7 0-7 0-7 0-7
*Registers 6 and 7 are not used.
Table XVII. Mode_A and Mode_B Registers for CCD Region Selection
Register Name SCP1 SCP2 SCP3 SCP4
Bit Width 8 8 8 8
Register Type Mode_Reg(2) Mode_Reg(3) Mode_Reg(3) Mode_Reg(3)
Range 0-255 lines 0-255 lines 0-255 lines 0-255 lines
Description Sequence Change Position 1 Sequence Change Position 2 Sequence Change Position 3 Sequence Change Position 4
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Special Vertical Sweep Mode Operation
The AD9898 contains a special mode of vertical timing operation called sweep mode. This mode is used to generate a continuous number of repetitive vertical pulses that span multiple HD lines. One example of when this mode may be needed is the start of the CCD readout operation. At the end of the image exposure, but before the image is transferred by the sensor gate pulses, the vertical interline CCD registers should be cleared of all charge. The charge can be shifted out quickly with a long series of pulses on the V1-V4 outputs. This operation will span multiple HD line lengths.
Normally the sequences are contained within one HD line length, but with the sweep mode enabled, the HD boundaries will be ignored until the region is finished. The special vertical sweep mode operation is only output in CCD Region0 and CCD Region3. (See Figures 33 and 34.) The SVREP_MODE register located at control Address 0x0A is used to enable and configure the special sweep mode operation as described in Table XVIII. The maximum number of repeats in each region is 2048 while operating in this mode using the SVREP0 and SVREP3 Mode_Reg(4) registers.
Table XVIII. Description of SVREP_MODE Register
SVREP_MODE 0 0 1 1 0 1 0 1
Description of Sweep Mode Operation Normal Vertical Timing Operation in All CCD Regions Special Vertical Sweep Mode Timing Output in CCD Region0 Only Special Vertical Sweep Mode Timing Output in CCD Region3 Only Special Vertical Sweep Mode Timing Output in CCD Region0 and CCD Region3
HD
V1-V4
Figure 31. NonOverlapping Example for Normal Vertical Timing Operation with SVREP_MODE = 0 and VTPREPx = 4
HD NOT OUTPUT BECAUSE THE 8TH REPETITION OVERLAPS WITH HD V1-V4
Figure 32. Overlapping Example for Normal Vertical Timing Operation with SVREP_MODE = 0 and VTPREPx = 8
SCP0 CCD REGION0 HD SCP1 = 3
0
1
2
0
V1-V4
Figure 33. Sweep Mode Timing Example with SVREP_MODE = 1 and SVREP0 = 28
SCP3 CCD REGION3 HD SCP4 = 3
0
1
2
0
V1-V4
Figure 34. Sweep Mode Timing Example with SVREP_MODE = 2 and SVREP3 = 28
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Table XIX. HD and VD Registers
Register Name SPAT_EN SPATLOGIC V1SPAT_TOG1 V1SPAT_TOG2 V2SPAT_TOG1 V2SPAT_TOG2 V3SPAT_TOG1 V3SPAT_TOG2 V4SPAT_TOG1 V4SPAT_TOG2
Bit Width 1 4 13 13 13 13 13 13 13 13
Register Type Control (Addr 0x0A) Control (Addr 0x0A) Mode_Reg(5) Mode_Reg(5) Mode_Reg(6) Mode_Reg(6) Mode_Reg(6 and 7) Mode_Reg(7) Mode_Reg(7) Mode_Reg(7 and 8)
Reference Counter
Range Pixels
Description SPAT Enable Control (0 = SPAT Disabled, 1 = SPAT Enabled) SPAT Logic Setting Polarity Change Position Start for V1 SPAT Polarity Change Position End for V1 SPAT Polarity Change Position Start for V2 SPAT Polarity Change Position End for V2 SPAT Polarity Change Position Start for V3 SPAT Polarity Change Position End for V3 SPAT Polarity Change Position Start for V4 SPAT Polarity Change Position End for V4 SPAT
ST ST ST ST ST ST ST ST
0-8192 0-8192 0-8192 0-8192 0-8192 0-8192 0-8192 0-8192
Special Vertical Timing (SPAT)
The AD9898 provides additional special vertical timing (SPAT) generation, which is output in the same line as the VSG pulse. The SPAT timing allows for configuring a second vertical output pulse in the VSG line. Tables XIX and XX list the registers used to generate the SPAT timing. Figures 35 and 36 show how the SPAT timing can be either an AND case or an OR case, depending on the value set in the SPATLOGIC register. As these figures show, the internal SPAT timing for the AND case will start High and then go Low at the first VxSPAT_TOG1 position. In the OR case, the internal
SPAT timing will initially start Low and then toggle High at the first VxSPAT_TOG1 position. This provides the ability to output the second vertical pulse when the internal Vx pulse is in both High and Low states.
Table XX. SPATLOGIC Register (Addr 0x0A)
SPATLOGIC [3:0] 3 2 1 0 V4 V3 V2 V1
Description 0 = OR, 1 = AND
VD
HD
13-BIT ST COUNTER (FIXED) INTERNAL V2 WITHOUT SPAT APPLIED INTERNAL SPAT TIMING FOR V2 WITH SPATLOGIC = 1
1
2
V2 OUTPUT WITH SPAT APPLIED
VSGx 1. THE VxSPAT_TOG1 AND VxSPAT_TOG2 REGISTERS REFERENCE THE 13-BIT ST COUNTER. 2. THE INTERNAL SPAT TIMING IS APPLIED IN THE SAME LINE AS THE VSGx PULSE. PROGRAMMABLE CLOCK POSITIONS 1. VxSPAT_TOG1 (PROGRAMMABLE AT MODE_REGs). 2. VxSPAT_TOG2 (PROGRAMMABLE AT MODE_REGs).
Figure 35. SPAT Example Applied to V2 with SPATLOGIC = xx1x
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HD
13-BIT ST COUNTER (FIXED) INTERNAL V1 WITHOUT SPAT APPLIED INTERNAL SPAT TIMING FOR V1 WITH SPATLOGIC = 0
1
2
V1 OUTPUT WITH SPAT APPLIED
VSGx 1. THE VxSPAT_TOG1 AND VxSPAT_TOG2 REGISTERS REFERENCE THE 13-BIT ST COUNTER. 2. THE INTERNAL SPAT TIMING IS APPLIED IN THE SAME LINE AS THE VSGx PULSE. PROGRAMMABLE CLOCK POSITIONS 1. VxSPAT_TOG1 (PROGRAMMABLE AT MODE_REGs). 2. VxSPAT_TOG2 (PROGRAMMABLE AT MODE_REGs).
Figure 36. SPAT Example Applied to V1 with SPATLOGIC = xxx0
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Table XXI. SUBCK Registers
Register Name SUBCKNUM SUBCKSUPPRESS SUBCK_EN
Bit Width Register Type 11 1 1 Control (Addr 0x0B) Control (Addr 0x01) Control (Addr 0x0B) Control (Addr 0x01) Control (Addr 0x0B) System_Reg(14) System_Reg(14) System_Reg(15) System_Reg(15) Mode_Reg(2)
Reference Counter
Range 0-2047 Pulses 0-1 Pulse
Description Number of SUBCK Pulses per Field Suppress First SUBCK after Last VSG Line Pulse SUBCK Output Enable Control (0 = Disable, 1 = Enable) High Speed Shutter Mode Operation High Speed Shutter SUBCLK Position/Number SUBCLK1 First Toggle Position SUBCLK1 Second Toggle Position SUBCLK2 First Toggle Position SUBCLK2 Second Toggle Position (0 = SUBCK1, 1 = SUBCK2)
SUBCKMODE_HP 1 SUBCKNUM_HP 3 SUBCK1TOG1 SUBCK1TOG2 SUBCK2TOG1 SUBCK2TOG2 SUBCKSEL 9 9 9 9 1
0-7 Pulses OL-Counter OL-Counter OL-Counter OL-Counter 0-511 Pixel Location 0-511 Pixel Location 0-511 Pixel Location 0-511 Pixel Location
ELECTRONIC SHUTTER TIMING CONTROL
CCD image exposure time is controlled through the use of the CCD substrate clock signal (SUBCK), which pulses the CCD substrate to clear out accumulated charge prior to the exposure period. The AD9898 supports three types of electronic shuttering: normal shutter mode, suppression shutter mode, and high speed shutter mode. Table XXI contains the registers required for programming SUBCK pulses for each of these modes.
Normal Shutter Mode
operating in this mode. As shown in Figure 37, the location of the additional SUBCK pulse is adjusted by setting the SUBCKNUM_HP register as described in Table XXII. Finer resolution of the exposure time is possible using this mode by adding a SUBCK pulse in the line, as shown in Figure 40.
Multiple Pulse Mode
Figure 37 shows the VD and SUBCK output for normal shutter mode. The SUBCK will pulse once per line. The number of SUBCK pulses per field can be programmed by setting register SUBCKNUM (Addr 0x0B). As shown in Figure 37, the SUBCK pulses will always begin on the line after the sensor gate occurs, specified by VSGACTLINE (Mode_Reg(1)).
SUBCK Suppression Mode
In addition to the normal operating SUBCK pulse, up to seven sequential SUBCK pulses can be applied within the same line while operating in this mode. As shown in Figure 41, the number of additional SUBCK pulses is selectable by setting SUBCKMODE_HP = 1 and the SUBCKNUM_HP registers as described in Table XXII.
Table XXII. Single and Multiple Pulse Mode
SUBCKMODE_HP 0 SUBCKNUM_HP 0 1 2 3 4 5 6 7 Single Pulse Mode Normal Shutter Mode Operation Position No. 1 Position No. 2 Position No. 3 Position No. 4 Position No. 5 Position No. 6 Position No. 7 1 Multiple Pulse Mode Normal Shutter Mode Operation 1 Additional Pulse 2 Additional Pulses 3 Additional Pulses 4 Additional Pulses 5 Additional Pulses 6 Additional Pulses 7 Additional Pulses
Normally the SUBCKs will begin to pulse on the line following the last sensor gate line (VSG). With some CCDs, the first SUBCK following the VSG line needs to be suppressed. The SUBCKSUPPRESS register allows for this suppression. The first SUBCK following the last VSG pulse is suppressed when SUBCKSUPPRESS = 1, as shown in Figure 38.
High Precision Shutter Mode
The high speed shutter mode can be operated in two different modes, single pulse and multiple pulse. These modes are set up by programming the SUBCKNUM_HP register and SUBCKMODE_HP register, as described in Table XXII and shown in Figures 40 and 41.
Single Pulse Mode
In addition to the normal operating SUBCK pulse, one additional SUBCK pulse can be applied within the HD line while
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VD HD VSG1- VSG2
t EXP
SUBCK 1 2 3
t EXP
SUBCK PROGRAMMABLE SETTINGS 1. SUBCK STARTING POLARITY IS ALWAYS HIGH. 2. FALLING EDGE OF SUBCK IS SET USING THE SUBCK1TOG1 OR SUBCK2TOG1 REGISTERS. 3. RISING EDGE OF SUBCK IS SET USING THE SUBCK1TOG2 OR SUBCK2TOG2 REGISTERS. NUMBER OF SUBCK PULSES WITHIN THE FIELD IS SET USING THE SUBCKNUM REGISTER. IN THIS EXAMPLE, SUBCKNUM = 2.
Figure 37. Normal Shutter Mode
VD
HD VSG1- VSG2
t EXP
SUBCK 1 SUBCK PROGRAMMABLE SETTINGS SETTING SUBCKSUPPRESS REGISTER = 1 SUPPRESSES THIS FIRST SUBCK FOLLOWING VSG PULSE.
t EXP
Figure 38. SUBCK Suppression Mode
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HD OLEN 9-BIT OL-COUNTER
SUBCK 1 NORMAL SHUTTER MODE PULSE ALWAYS OUTPUT 2 3 4 5 6 7
Figure 39. Electronic Shutter Timing
HD
9-BIT OL-COUNTER
SUBCK 1
Figure 40. Electronic Shutter Timing Example with SUBCKMODE_HP = 0 and SUBCKNUM_HP = 1
HD
9-BIT OL-COUNTER
SUBCK 1 2 3
Figure 41. Electronic Shutter Timing Example with SUBCKMODE_HP = 1 and SUBCKNUM_HP = 3
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VSG TIMING
The VSG timing is controlled using the registers in Table XXIII. Two unique preprogrammed VSG pulses can be configured using the VSGTOG1_x (x = 0, 1) registers. As shown in Figure 42, the period of the VSG pulse is set by programming the VSGLEN register. The VSGSELx (x = 0, 1) can then be used to point to either the VSGTOG1_0 or VSGTOG1_1 pulse.
Figure 42 also shows an example of the VSG pulse being output in the fourth line by setting the VSGACTLINE = 3. The VSG1 and VSG2 pulses reference the 13-bit fixed ST counter, which starts counting from the line set in the VSGACTLINE register. The 13-bit counter allows for overlapping of the VSG pulse into the next line, if needed.
Table XXIII. VSG Registers
Register Name VSGMASK
Bit Width 6
Register Type Control (Addr 0x0A)
Reference Counter
Range
Description VSG Mask Control (00 = VSG1 masked, VSG2 masked) (02 = VSG1 not masked, VSG2 masked) (08 = VSG1 masked, VSG2 not masked) (0A = VSG1 not masked, VSG2 not masked) VSG Output Enable Control (0 = Disable VSG Outputs, 1 = Enable VSG Outputs) VSG Sequence 1, Toggle Position 1 VSG Sequence 2, Toggle Position 1 VSG Pulsewidth VSG1 Output Selector (0 = VSGTOG1_0 applied on VSG1 output, 1 = VSGTOG1_1 applied on VSG1 output) VSG2 Output Selector (0 = VSGTOG1_0 applied on VSG2 output, 1 = VSGTOG1_1 applied on VSG2 output) VSG Active Line
VSG_EN
1
Control (Addr 0x0B)
High/Low
VSGTOG1_0 VSGTOG1_1 VSGLEN VSGSEL0
11 11 8 1
Sys_Reg(13) Sys_Reg(13) Sys_Reg(14) Mode_Reg(1)
ST ST ST
0-8191 Pixels 0-8191 Pixels 0-255 Pixels High/Low
VSGSEL1
1
Mode_Reg(1)
High/Low
VSGACTLINE
7
Mode_Reg(1)
0-128 Lines
VD
HD 0 13-BIT ST COUNTER (FIXED) VSGACTLINE VSGx 1. VSGTOG1_x (x = 0, 1) REFERENCES THE 13-BIT ST COUNTER. 2. VSGACTLINE (PROGRAMMABLE AT MODE_REG (1)). 3. VSGLEN (PROGRAMMABLE AT SYS_REG (14)). PROGRAMMABLE CLOCK POSITION VSGTOG1_x (PROGRAMMABLE AT SYS_REG (13)). VSGLEN 1 1 2 3
Figure 42. Example of VSG Pulse
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VSUB CONTROL VSUB Placement and Polarity
The CCD readout bias (VSUB) can be programmed to accommodate different CCDs. VSUB ON and OFF toggle positions and polarity are controlled using VSUBTOG (Addr 0x0D) and VSUBPOL (Addr 0x0D) registers, respectively, as described in Table XXIV. Since the VSUBTOG is an 11-bit register, the VSUB ON position is programmable within any line. Figure 43 shows an example of controlling VSUB using these registers.
Table XXIV. VSUB Registers
Figure 43 shows the sequence of events for programming the VSUB ON and OFF toggle positions and polarity. 1. Program VSUBTOG = 2 and VSUBPOL = 1. 2. Since VSUBTOG and VSUBPOL are VD synchronous type registers, the falling edge of VD will update the serial writes from Step 1 here. 3. VSUB will be asserted high after two HD cycles. 4. Program VSUBTOG = 3 and VSUBPOL = 0. 5. Since VSUBTOG and VSUBPOL are VD synchronous type registers, the falling edge of VD will update the serial writes from Step 4 here. 6. VSUB will be asserted low after three HD cycles.
Register Name
Bit Register Range Width Type (Lines) Description Control Control (0 = Low, 1 = High) 0-2048 VSUB Toggle Position
VSUBPOL 1 VSUBTOG 11
1 SERIAL WRITES 2 VD
4
5
HD 3 VSUB 2 LINES 3 LINES 6
Figure 43. VSUB Timing Example
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MSHUT CONTROL MSHUT Basic Operation
The AD9898 provides an MSHUT output pulse that can be configured to control the mechanical shutter of the camera. The registers used to control the MSHUT pulse are listed in Table XXV. The MSHUT pulse can be placed at the start of any line by using the 11-bit MSHUTPOS register. The MSHUT pulsewidth is controlled using the MSHUTLEN register.
The AD9898 offers four preprogrammed MSHUT patterns that are selectable using the MSHUTPAT register. The preprogrammed length is the same for all patterns set by the MSHUTLEN register, but the active ON period of the MSHUT pulse is different for each pattern, as shown in Figure 44. Figure 45 shows an example of selecting MSHUTPAT0 positioned to start three lines after the falling edge of VD with MSHUTLEN = 5.
Table XXV. MSHUT and STROBE Registers
Register Name MSHUTPAT
Bit Width 2
Register Type Control (Addr 0x01)
Description Selects MSHUT Pattern (See Figure 44) (0 = MSHUTPAT0, 1 = MSHUTPAT1, 2 = MSHUTPAT2, 3 = MSHUTPAT3) MSHUT Initialize (1 = MSHUT Output Held LOW, 0 = Normal Operation Resumes) MSHUT Control (0 = MSHUT Held at Last State, 1 = MSHUT Output Enabled for Normal Operation) MSHUT Position during Normal Operation MSHUT Position during High Precision Operation MSHUT Pattern Length (See Figures 44 and 45) STROBE Output Enable Control (0 = STROBE Output Held Low, 1 = Enable STROBE Output)
MSHUTINIT MSHUTEN MSHUTPOS MSHUTPOS_HP MSHUTLEN STROBE_EN
1 1 11 3 8 1
Control (Addr 0x0C) Control (Addr 0x0C) Control (Addr 0x0C) Control (Addr 0x0C) Sys_Reg(13) Control (Addr 0x0B)
HD
MSHUTPAT0
MSHUTPAT1
MSHUTPAT2 MSHUTPAT3 MSHUTLEN + 1
Figure 44. MSHUT Patterns Available by Setting MSHUTPAT Register
VD
HD VSG1- VSG2 SUBCK MSHUT
1
2
3
1
2
3
4
5
6
t EXP
MSHUTPOS = 3
MSHUTPAT = 0, MSHUTLEN = 5
Figure 45. Example of MSHUT Timing with MSHUTEN = 1 and MSHUTPOS_HP = 0
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MSHUT High Precision Operation
The MSHUTPOS_HP register allows more precise control of the MSHUT position within a line. Under normal MSHUT operation when MSHUTPOS_HP = 0, the MSHUT polarity changes from high to low on the negative edge of the HD pulse, as shown in Figure 44. By using the MSHUTPOS_HP register, the rising and falling edges of MSHUT can be delayed by multiples of the OL counter length, which has been set in the OLEN
register. For example, if MSHUTPOS_HP = 3, the MSHUT rising and falling edges will be delayed by three OL counter cycles after the falling edge of HD, as shown in Figure 46. Figure 46 provides an example of high precision MSHUT and SUBCK timing. In this example, the length of the OL counter is shorter. This provides very precise control of the placement of the MSHUT pulse within a line.
VD
HD VSG1- VSG2 SUBCK
1
2
3
1
2
3
4
5
6
t EXP
OL COUNTER
MSHUT
MSHUTPOS = 3
OL COUNTER OL OL COUNTER COUNTER
MSHUTPAT = 0, MSHUTLEN = 5
Figure 46. Example of MSHUT High Precision Timing--MSHUTEN = 1 and MSHUTPOS_HP = 3
VD
HD VSG1- VSG2 SUBCK MSHUT1 MSHUT2
1
2
3
1
2
3
4
5
6
t EXP
DELAY = 3 OL COUNTER LENGTHS MSHUTPOS = 3 MSHUTPAT = 0, MSHUTLEN = 5
NOTES 1MSHUT OUTPUT IN NORMAL OPERATION WITH MSHUTPOS_HP = 0 2MSHUT OUTPUT IN HIGH PRECISION OPERATION WITH MSHUTPOS_HP = 3
Figure 47. Example of MSHUT High Precision Timing--MSHUTEN = 1, MSHUTPOS_HP = 3, with SUBCKMODE_HP = 1, SUBCKNUM_HP = 3
REV. 0
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AD9898
STROBE Control
The AD9898 provides a STROBE output pulse that can be used to trigger the camera flash circuit. STROBE operation is set by only one register, as described in Table XXV. The STROBE output is held Low when STROBE_EN (Addr 0x0B) is set to 0 and enabled when set to 1. Providing STROBE_EN = 1, the STROBE output pulse will be asserted High on the rising edge of the last SUBCK pulse in the field, as shown in Figure 48. Figure 48 also shows the STROBE pulse asserted Low again on the rising edge of VSG.
SLAVE AND MASTER MODE OPERATION
SLAVE_MODE register (Addr 0xD6) can be used to configure the AD9898 into master mode by setting SLAVE_MODE = 0.
Slave Mode Operation
While operating in slave mode, VD, HD, and VGATE are provided externally from the image processor. VGATE is input active high on Pin 45. Unlike master mode operation, there is a 7 CLI clock cycle delay from the falling edge of HD to when the 12-bit gray code H counter is reset to zero (see Figure 49).
Master Mode Operation
The AD9898 can be operated in either slave mode or master mode. It defaults to the slave mode operation at power-up. The
SET STROBE_EN (ADDR 0x0B) = 1
While operating in master mode, VD and HD are outputs and the SYNC/VGATE pin is configured as an external SYNC input. Master mode is selected by setting register SLAVE_MODE (Addr 0xD6) = 0.
VD
VSG1- VSG2
t EXP
SUBCK
STROBE 1
1. STROBE OUTPUT ASSERTED HIGH ON RISING EDGE OF LAST SUBCK PULSE. 2. STROBE OUTPUT ASSERTED LOW ON NEGATIVE EDGE OF VSG PULSE.
2
Figure 48. STROBE Output Timing
VD
HD 3ns MIN CLI H-GRAY CODE COUNTER X (PIXEL COUNTER)
H-COUNTER RESET
H-COUNTER RESET
X
X
X
X
X
X
X
X
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
0
1
2
3
4
INTERNAL 12-BIT H-GRAY CODE COUNTER IS RESET 7 CLOCK CYCLES AFTER THE HD FALLING EDGE.
Figure 49. External VD/HD and Internal 12-Bit H-Gray Code Counter Synchronization, SLAVE Mode
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REV. 0
AD9898
VARIABLE GAIN AMPLIFIER Optical Black Clamp
The VGA provides a gain range of 6 dB to 40 dB, programmable with 10-bit resolution through the serial digital interface. The minimum gain of 6 dB is needed to match a 1 V input signal with the ADC full-scale range of 2 V. The VGA gain curve follows a linear-in-dB characteristic. The exact VGA gain can be calculated for any gain register value using the equation Gain = (0.035 x Code) + 5.3 where the code range is 0 to 1023. Figure 50 shows a typical AD9898 VGA gain curve.
42
The optical black clamp loop is used to remove residual offsets in the signal chain and to track low frequency variations in the CCD's black level. During the optical black (shielded) pixel interval on each line, the ADC output is compared with a fixed black level reference, selected by the user in the clamp level register. Any value between 0 LSB and 63 LSB may be programmed with 6-bit resolution. The resulting error signal is filtered to reduce noise, and the correction value is applied to the ADC input through a D/A converter. Normally the optical black clamp loop is turned on once per horizontal line, but this loop can be updated more slowly to suit a particular application. The optical black clamp is controlled by the CLPOB signal, which is fully programmable (see Horizontal Clamping and Blanking section). System timing examples are shown in the Horizontal Timing Sequence Example section. The CLPOB pulse should be placed during the CCD's optical black pixel. It is recommended that the CLPOB pulse duration be at least 20 pixels wide. Shorter pulsewidths may be used, but the ability to track low frequency variations in the black level will be reduced.
A/D Converter
36
VGA GAIN (dB)
30
24
18
12
The AD9898 uses a high performance 10-bit ADC architecture, optimized for high speed and low power. Differential nonlinearity (DNL) performance is typically better than 0.5 LSB. The ADC uses a 2 V input range. Better noise performance results from using a larger ADC full-scale range.
0 127 255 383 511 639 767 VGA GAIN REGISTER CODE 895 1023
6
Digital I/O States for Different Operating Conditions
Figure 50. VGA Gain Curve
Table XXVI describes the state of the digital I/Os for different operating conditions.
Table XXVI. I/O Levels
I/O DCLK1 DCLK2 VD2 HD2 RG H1 H2 V1 V2 V3 V4 SUBCK VSG1 VSG2 STROBE MSHUT FD
OCONT_REG1= 0 ACTIVE ACTIVE H H L H L H H H H H H H L L H
SW_RESET ACTIVE ACTIVE H H L H L L L L H H L H L L L
DIGSTBY L L H H L H L H L L H H H H L L L
SYNC ACTIVE ACTIVE H H ACTIVE ACTIVE ACTIVE FREEZE FREEZE FREEZE FREEZE FREEZE FREEZE FREEZE FREEZE FREEZE FREEZE
NOTES 1 OUTCONT_REG is a register setting located at Addr 0x05. It defaults to 0 at power-up. 2 VD and HD operating in master mode.
REV. 0
-45-
AD9898
VDD (INPUT) CLI (INPUT)
1
2
OUTCONT1 (INTERNAL SIGNAL)
t PWR
SERIAL WRITES
4
5
6
7
8
9
10
1V
VD (OUTPUT)
ODD FIELD
1H
EVEN FIELD
ODD FIELD
HD (OUTPUT)
H1, V1, V2, V3, VSG1, VSG2, VSUB, SUBCK, FD
DIGITAL OUTPUTS
H2, RG, MSHUT, STROBE
t DELAY3
DCLK22 (OUTPUT)
DCLK1 (OUTPUT)
t SETTLING4
NOTES 1OUTCONT IS AN INTERNAL SIGNAL CONTROLLED USING REGISTER OUTCONT_REG (ADDR 0x05). 2DCLK2 WILL BE OUTPUT ON FD/DLCK2, PIN 16, PROVIDING REGISTER DCLK2SEL (ADDR 0xD5) = 1. 3IT TAKES 11 CLI CLOCKS FROM WHEN OUTCONT GOES HIGH UNTIL VD, HD, AND DIGITAL OUTPUT DATA IS VALID. 4THERE IS 500 s SETTLING TIME FROM WHEN THE DIGSTBY REGISTER IS SET TO WHEN THE DLCK1 IS STABLE.
Figure 51. Recommended Power-Up Sequence and Synchronization, Master Mode
POWER-UP Recommended Power-Up Sequence for Master Mode
When the AD9898 is powered up, the following sequence is recommended. (Refer to Figure 51 for each step.) 1. Turn on power supplies for AD9898. 2. Apply the CLI master clock input. CLI will be output on DCLK2 (Pin 16) at this time. 3. Reset the internal AD9898 registers. Write a 0x000000 to the SW_RESET register (Addr 0x00). This will set all internal register values to their default values. (This step is optional because an internal power-on reset circuit is applied at power-up.) 4. Program the DIGSTBY and AFESTBY registers (Addr 0x05) = 1, and program all other necessary control registers.
Program system registers (Addr 0x14). Program Mode_A registers (Addr 0x15). Program Mode_B registers (Addr 0x16). Program OUTCONT_REG register (addr 0x05) = 1. (The internal OUTCONT signal will be asserted high at this time and will enable the digital outputs.) 9. Program control register MODE (Addr 0x0A) = 0. This selects Mode_A operation. (This step is optional because the AD9898 defaults to Mode_A at initial power-up.) 10. Program control register MODE (Addr 0x0A) = 1. This selects Mode_B operation. Complete this write at least four CLI cycles before start of the next field.
5. 6. 7. 8.
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REV. 0
AD9898
VDD (INPUT)
CLI (INPUT)
OUTCONT (INTERNAL SIGNAL)
1
2
3
5
6
SERIAL WRITES
VD (OUTPUT)
HD (OUTPUT)
H1, V1, VSG1, VSG2, VSUB, SUBCK
DIGITAL OUTPUTS
H2, V2, V3, FD, RG, MSHUT, STROBE
tDELAY2
DCLK1 AND DCLK21
AFESTBY (REGISTER)
DIGSTBY (REGISTER)
NOTES 1DCLK2 WILL BE OUTPUT ON FD/DLCK2, PIN 16, PROVIDING REGISTER DCLK2SEL (ADDR 0xD5) = 1.
2IT
TAKES 11 CLI CLOCKS FROM WHEN OUTCONT GOES HIGH UNTIL VD, HD, AND DIGITAL OUTPUT DATA IS VALID.
Figure 52. Recommended Standby Sequence
STANDBY MODE OPERATION Recommended Standby Mode Sequence
When the AD9898 is going into standby operation, the following sequence is recommended. (Refer to Figure 52 for each step.) 1. Program OUTCONT_REG (Addr 0x05) = 0. This will assert the internal OUTCONT signal LO causing all digital outputs to become disabled. 2. Program registers AFESTBY (Addr 0x05) = 0 and DIGSTBY (Addr 0x05) = 0. The AD9898 is then in standby operation.
3. When it is time to come out of standby operation, program register DIGSTBY (Addr 0x05) = 1 and register AFESTBY (Addr 0x05) = 1. 4. Program necessary control registers. 5. Program control register MODE (Addr 0x0A) = 0. This selects Mode_A operation. 6. Program register OUTCONT_REG (Addr 0x05) = 1. This will assert the internal OUTCONT signal high, causing all digital outputs to become active.
REV. 0
-47-
AD9898
VDD (INPUT) 4
CLI (INPUT)
OUTCONT (INTERNAL)
SERIAL WRITES
VD (OUTPUT)
ODD FIELD
EVEN FIELD
ODD FIELD
HD (OUTPUT)
H1, V1, V2, V3, V4, VSG1, VSG2, VSUB, FD, SUBCK ,
DIGITAL OUTPUTS
H2, RG, MSHUT, STROBE
DCLK1
DCLK2*
AFESTBY (REGISTER)
DIGSTBY (REGISTER) *DCLK2 WILL BE OUTPUT ON FD/DLCK2, PIN 16, PROVIDING REGISTER DCLK2SEL (ADDR 0xD5) = 1.
Figure 53. Recommended Power-Down Sequence
POWER-DOWN MODE OPERATION Recommended Power-Down Sequence
When the AD9898 is going to be powered down, the following sequence is recommended. (Refer to Figure 53 for each step.) 1. Program OUTCONT_REG (Addr 0x05) = 0. 2. Program registers AFESTBY (Addr 0x05) = 0 and DIGSTBY (Addr 0x05) = 0. 3. Remove power from the AD9898.
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AD9898
HORIZONTAL TIMING SEQUENCE EXAMPLE
Figure 54 shows a sample CCD layout. The horizontal register contains 28 dummy pixels, which will occur on each line clocked from the CCD. In the vertical direction, there are 10 optical black (OB) lines at the front of the readout and two at the back. The horizontal direction has four OB pixels in the front and 48 in the back. To configure the AD9898 horizontal signals for this CCD, three sequences can be used. Figure 55 shows the first sequence to be used during vertical blanking. During this time, there are no
valid OB pixels from the sensor, so the CLPOB is not used. In some cases, if the horizontal clocks are used during this time, the CLPOB signal may be used to keep the AD9898's clamp partially settled. Figure 56 shows the recommended sequence for the vertical OB interval. The clamp signal is used across the whole line in order to stabilize the clamp loop of the AD9898. Figure 57 shows the recommended sequence for the effective pixel readout. The 48 OB pixels at the end of each line are used for the CLPOB signal.
SEQUENCE 2 (OPTIONAL)
2 VERTICAL OB LINES
V
EFFECTIVE IMAGE AREA
USE SEQUENCE 3
10 VERTICAL OB LINES
USE SEQUENCE 2 H 4 OB PIXELS 48 OB PIXELS HORIZONTAL CCD REGISTER
28 DUMMY PIXELS
Figure 54. Sample CCD Configuration
SEQUENCE 1: VERTICAL BLANKING
CDIN
INVALID PIX
VERTICAL SHIFT
DUMMY
INVALID PIXELS
VERT SHIFT
SHP
SHD H1
H2
HD
CLPOB
CLPOB PULSE MAY BE USED DURING HORIZONTAL DUMMY PIXELS IF THE H-CLOCKS ARE USED DURING VERTICAL BLANKING.
Figure 55. Horizontal Sequence during Vertical Blanking
REV. 0
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AD9898
SEQUENCE 2: VERTICAL OPTICAL BLACK LINES CCDIN OPTICAL BLACK
VERTICAL SHIFT DUMMY OPTICAL BLACK VERT SHIFT
SHP
SHD
H1
H2
HD
CLPOB
Figure 56. Horizontal Sequence during Vertical Optical Black Pixels
SEQUENCE 3: EFFECTIVE PIXEL LINES
OB
CCDIN
OPTICAL BLACK
VERTICAL SHIFT
DUMMY
EFFECTIVE PIXELS
OPTICAL BLACK
VERT SHIFT
SHP
SHD
H1 H2
HD
CLPOB
Figure 57. Horizontal Sequences during Effective Pixels
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REV. 0
AD9898
CIRCUIT LAYOUT INFORMATION
The AD9898 typical circuit connection is shown in Figure 58. The PCB layout is critical to achieving good image quality from the AD9898. All of the supply pins, particularly the AVDD, TCVDD, RGVDD, and HVDD supplies, must be decoupled to ground with good quality high frequency chip capacitors. The decoupling capacitors should be located as close as possible to the supply pins and should have a very low impedance path to a continuous ground plane. There should also be a 4.7 F or larger value bypass capacitor for each main supply--AVDD, RGVDD, HVDD, and DRVDD--although this is not necessary for each individual pin. For most applications, it is easier to share the supply for RGVDD and HVDD, which may be done as long as the individual supply pins are separately bypassed. A separate 3 V supply may also be used for DRVDD, but this
supply pin should still be decoupled to the same ground plane as the rest of the chip. A separate ground for DRVSS is not recommended. The analog bypass pins (REFB, REFT) also should be carefully decoupled to ground as close as possible to their respective pins. The analog input (CCDIN) capacitor also should be located close to the pin. The H1, H2, and RG traces should be designed to have low inductance to avoid excessive distortion of the signals. Heavier traces are recommended because of the CCD's large transient current demand on H1 and H2. When possible, physically locating the AD9898 closer to the CCD will reduce the inductance on these lines. As always, the routing path should be as direct as possible from the AD9898 to the CCD.
3V ANALOG SUPPLY 0.1 F
3V DRIVER SUPPLY 10k
VSUB TO CCD EXTERNAL SYNC FROM ASIC/DSP OUTCONT
SYNC/VGATE
7
V1-V4 VSG1, VSG2 SUBCK TO V-DRIVER
SUBCK
DVDD
OUTCONT
VSUB
DVSS
VSG2
VSG1
V4
V3
V2
V1
3
SCK SL SDATA REFB 1.0 F REFT AVSS CCDIN AVDD CLI TCVDD TCVSS 0.1 F RGVDD 0.1 F
48
47
46 45
44 43 42
41 40
39 38 37 36
SERIAL INTERFACE
D0 1 D1 2 D2 3 D3 4 D4
5 6 7 8 9 10 11
PIN 1 IDENTIFIER
35 34 33
32
1.0 F 0.1 F CCD SIGNAL INPUT CLOCK 3V ANALOG SUPPLY 0.1 F
3V DRIVER SUPPLY
DRVSS
4.7 F
0.1 F
AD9898
TOP VIEW (Not to Scale)
31 30 29 28 27 26 25
DRVDD
D5 D6 D7 D8
D9 12
DCLK1
H2
H1
RGVSS
HVSS
MSHUT
STROBE
FD/DCLK2
DCLK1, FD/DCLK2, HD, VD TO MECHANICAL SHUTTER CIRCUIT TO STROBE CIRCUIT
4
HVDD
RG
HD
VD
DATA OUTPUTS
10
13
14
15 16
17 18 19
20 21
22 23 24
4.7 F
3V ANALOG SUPPLY
3
H2, H1, RG
3V ANALOG SUPPLY
0.1 F
Figure 58. Typical Circuit Configuration
REV. 0
-51-
AD9898
OUTLINE DIMENSIONS 48-Lead Lead Frame Chip Scale Package [LFCSP] (CP-48)
Dimensions shown in millimeters
7.00 BSC SQ
0.60 MAX 0.60 MAX
37 36
0.30 0.23 0.18
48 1
PIN 1 INDICATOR
PIN 1 INDICATOR
TOP VIEW
6.75 BSC SQ
BOTTOM VIEW
5.25 5.10 SQ 4.95
0.50 0.40 0.30 1.00 MAX 0.65 NOM 0.05 MAX 0.02 NOM 0.50 BSC SEATING PLANE COPLANARITY 0.08
25 24
12 13
0.25 MIN 5.50 REF
1.00 0.90 0.80 0.20 REF
12 MAX
COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2
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REV. 0
C02877-0-5/03(0)

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